Air-gap formation during IMD deposition to lower interconnect capacitance

Shieh, B.; Saraswat, Krishna C.; McVittie, J.P.; List, S.; Nag, Somnath; IslamRaja, M. M.; Havemann, R.H.

doi:10.1109/55.650339

Cited by 60 publications

(23 citation statements)

References 2 publications

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“…Previous reports have explored the role of air-gap structures in lowering line capacitance [3][4][5][6][7][8][9]. When depositing SiO 2 , air-gaps or voids can be formed between metal lines.…”

Section: Background 21 Capacitance Reduction Using Air Gap Structuresmentioning

confidence: 99%

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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In this study, we are pursuing an ultra low-loss interconnect pathway for 3D chip-chip connectivity, incorporating air-clad planar interconnects, air-clad TSVs, and gradual vertical-horizontal transitions. The motivation is to create an air-gap technology that offers the lowest possible effective k-value and near zero loss tangent minimizing the dielectric loss. The design and modeling of air-gap interconnection is presented. The fabrication challenges in airclad interconnect lines are discussed. A monolithic inverted air-gap horizontal transmission line structure is proposed as a means for further decreasing the dielectric loss. Extension of air-clad TSV technology for optical transmission is briefly discussed. IntroductionModern electronic systems are composed of a dense fabric of interconnect lines that connect electronic devices and chips. The scaling of transistors has resulted in miniaturization of individual devices and their interconnects. Smaller crosssectional area of electrical interconnects results in higher signal attenuation and makes data and clock recovery complex. High-speed interconnects have two primary loss mechanisms, namely metallic skin effect losses and dielectric losses. Skin effect loss is a phenomenon where, at high frequencies, the current is crowded into the near-surface region of the metal around the periphery of the conductor. As a result, the effective AC resistance per unit length of conductor increases with frequency. The second loss mechanism deals with dielectric losses. Dielectric losses are directly proportional to frequency and are therefore more pronounced at higher frequencies. Also, resistive losses in the return ground path cannot be ignored and are determined by the geometry and materials constituting the return path. Overall, dielectric losses dominate at frequencies above several GHz [1-2], as shown in Figure 1. This figure was produced with data from the International Technology Roadmap for Semiconductors (ITRS) for signal frequencies up to 50 GHz. As shown in Figure 1, the dielectric loss is more than twice that of the conductor loss at 20 GHz and the dielectric loss becomes more dominant at frequencies above 20 GHz. Thus, in order to achieve meaningful reduction in signal attenuation it is important to find ways to mitigate the dielectric loss at high frequencies. One way of achieving this goal is to use better interconnect and substrate materials.

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Section: Background 21 Capacitance Reduction Using Air Gap Structuresmentioning

confidence: 99%

Design and fabrication of ultra low-loss, high-performance 3D chip-chip air-clad interconnect pathway

Uzunlar

Sharma

Saha

et al. 2013

2013 IEEE 63rd Electronic Components and Technology Conference

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show abstract

“…A few technology nodes later and at the same time as Cu interconnects were developed, it is amazing to observe that what was considered as an issue was reversed to develop air gap architectures and evaluate air cavities introduction within Al metal lines [5][6][7]. For instance, Ueda et al [5] demonstrated that effective dielectric constant lower than 2 could be achieved.…”

Section: Architectures and Integration Schemes For The Fabrication Ofmentioning

confidence: 99%

Advanced Cu interconnects using air gaps

Gosset

Farcy

Pontcharra

et al. 2005

Microelectronic Engineering

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“…Applications include use in photonics and in semiconductor devices as ultra low-k dielectrics [5], and nanofluidic channels in chip based bio/chemical analysis [8]. Formation techniques for air gap structures can be classified into two groups: 1) formation between metal lines via CVD deposition [9], and 2) use of sacrificial materials as ''place-holders'' providing a temporary support layer for the interlevel dielectric and is subsequently removed either by etching or thermal decomposition [10]. The use of sacrificial materials is the preferred method as it allows for the complete removal of the intermetal dielectric within the gap and provides greater control of the gap shape.…”

Section: Introductionmentioning

confidence: 99%