AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Lourenço, Nuno; Martins, Ricardo; Canelas, António; Póvoa, Ricardo; Horta, Nuno

doi:10.1016/j.vlsi.2016.04.009

Cited by 54 publications

(16 citation statements)

References 21 publications

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“…Analogue circuit design can be divided into three steps [4]: topology selection, parametric optimisation and layout generation. First, the designer selects an appropriate circuit topology among various possible topologies for a particular application.…”

Section: Introductionmentioning

confidence: 99%

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

Anisheh

Shamsi

2018

IET Circuits, Devices & Systems

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This study presents a new placement and routing method for analogue integrated circuit layout generation based on an evolutionary algorithm, which is called modified cuckoo optimisation algorithm. Layout parasitic effects are taken into account to ensure that the performance of the circuit is not deteriorated. In order to verify the performance of the proposed method, layouts of three different circuits including differential to single-ended amplification stage, two-stage and three-stage operational amplifiers (op-amps) are automatically generated in a 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show the efficiency of the proposed algorithm in the analog layout generation.

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Section: Introductionmentioning

confidence: 99%

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

Anisheh

Shamsi

2018

IET Circuits, Devices & Systems

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“…The various layout aware design methodologies were proposed to analyse MOS characteristics and the circuit performance under LDEs [5][6][7][8][21][22][23][24]. An accurate and efficient finite-element method-based stress simulator has been developed to characterise the influence of STI stress on the performance of RF and analogue circuits by considering detailed layout and process information [5].…”

Section: Introductionmentioning

confidence: 99%

“…In the designs proposed in [5][6][7][8][21][22][23][24], the number of fingers was varied on a trial and error basis until the design specifications are met. Apparently, redesigning the circuit and redrawing the layout at each iteration is the major drawback of these procedures.…”

Section: Introductionmentioning

confidence: 99%

Design procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effect

Veldandi

Aahmed

2018

IET Circuits, Devices & Systems

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Nanoscale complementary metal-oxide-semiconductor (CMOS) circuit design extensively employs multifinger layout technique to alleviate the performance degrading parasitic and mismatch effects that are typically observed with single-finger layout. However, a continuous increase in the number of fingers accompanied by a simultaneous decrease in their finger width could lead to the penalty of a higher degree of variation in the MOSFET's small-signal parameters. It is due to the heightened shallow trench isolation (STI) stress that gets developed in such devices. The optimisation of circuit performance with the arbitrarily fixed number and width of fingers would be ambiguous. In this work, an analysis of current-voltage (I-V) characteristics of a MOSFET as a function of number of fingers has been proposed. It was found that both the drain current and gate transconductance get affected by the number of fingers. The authors proposed a Miller-compensated two-stage [operational transconductance amplifier (OTA)] and common source amplifier by considering STI effect. It is also found that the parameters of the proposed design matched well with the set of desired specifications. Also, the area of multifinger MOSFET OTA is lowered by up to 60% relative to that from the conventional. All post-layout simulations were performed using standard UMC 65 nm CMOS technology.

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“…Several analog design tools have been proposed in the literature from the eighties to now (EL-TURKY; PERRY, 1989;ANTREICH et al, 2000;STEFANOVIC;KAYAL, 2009;SEVERO et al, 2012;WEBER, 2015;LOURENÇO et al, 2016) but the analog design are still predominately performed using manual approach, some CAD tools to the schematic and layout draw, electrical simulators, design rule checks and post-layout parasitic extractions. The circuit sizing step is, in general, performed first by a hand simplified equation analysis (RAZAVI, 2001;ALLEN;HOLBERG, 2002) or some biasbased look-up tables (JESPERS; MURMANN, 2017) to obtain the preliminary device sizes.…”

Section: Design Methodology For Ulv Circuitsmentioning

confidence: 99%

“…The use of only W and L parameters as design variables is essential in general purpose tools, such as the UCAF tool, because no more information is needed from the circuit under design and it can be seen by the design tool as a black box. Due to its flexibility, the use of only transistor sizes as design variables is also widely used on other tools presented in the literature (WEBER, 2015;LOURENÇO et al, 2016;PHELPS et al, 2000).…”

Section: Ulv Circuit Design Using the Ucaf Toolmentioning

confidence: 99%

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

Severo¹

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I would like to thanks to Professor Wilhelmus Adrianus Maria Van Noije for the opportunity in work as a Ph.D. candidate at the Polytechnic School of the University of São Paulo and by all the challenges imposed to me that have collaborated significantly in the improvements of my professional abilities. I would like to thanks to the Federal University of Pampa for the opportunity of being on leave from the university by 3.5 years that made possible working full time in the Ph.D. studies and to the CNPq research agency for support to this work. I would also like to thanks to professors João A. Martino e Paula G. Der Agopian for all the help in the CMOS transistor characterization, to the IMEC Free-mini@asic and to the MOSIS Educational programs for the free integrated circuit fabrications and to professors João N. Soares Júnior and Márcio C. Schneider for all the suggestions gave me at the qualification exam. I would like to thanks to all the members of the DMPSV department of the LSI at USP, especially to Silvana, for all the conversations at the coffee time and commemoration during my stay in São Paulo. Finally, I thanks to my wife Tanísia for all the help and understanding during this shortage of time phase of my life.

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AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation

Cited by 54 publications

References 21 publications

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

Placement and routing method for analogue layout generation using modified cuckoo optimisation algorithm

Design procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effect

Filtros RC-Ativo ULV e ULP combinando OTA de único estágio e transcondutância negativa de entrada para receptores RF de baixa energia.

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