AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs

Huang, Lin; Xu, Qiang

doi:10.1109/date.2010.5457238

Cited by 20 publications

(30 citation statements)

References 22 publications

(38 reference statements)

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“…Quite a few research works were directed towards evaluating a single core's MTTF [2]. This was later extended for MTTF evaluation of an MPSoC employing multiple cores [8]. A parallel research direction is to optimize system MTTF at the application mapping phase assuming constant failure rate for cores [9].…”

Section: Introductionmentioning

confidence: 99%

Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems

Das

Kumar

Veeravalli

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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Abstract-Shrinking transistor geometries, aggressive voltage scaling and higher operating frequencies have negatively impacted the lifetime reliability of embedded multi-core systems. In this paper, a convex optimization-based task-mapping technique is proposed to extend the lifetime of a multiprocessor systems-onchip (MPSoCs). The proposed technique generates mappings for every application enabled on the platform with variable number of cores. Based on these results, a novel 3D-optimization technique is developed to distribute the cores of an MPSoC among multiple applications enabled simultaneously. Additionally, reliability of the underlying network-on-chip links is also addressed by incorporating aging of links in the objective function. Our formulations are developed for directed acyclic graphs (DAGs) and synchronous dataflow graphs (SDFGs), making our approach applicable for streaming as well as non-streaming applications. Experiments conducted with synthetic and real-life application graphs demonstrate that the proposed approach extends the lifetime of an MPSoC by more than 30% when applications are enabled individually as well as in tandem.

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Section: Introductionmentioning

confidence: 99%

Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems

Das

Kumar

Veeravalli

2013

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2013

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“…As long as the usage strategy of the representative period is consistent of system's service life, we can use degradation rate Ω to predict NBTI-induced degradation at any time t of its service lifetime. Unlike [15], wherein the aging rate Ω represents a high level aging effect, in this work, we propose to extract the NBTI-induced degradation rate at transistor level considering various runtime parameters variations, and estimate the long term NBTI-induced delay degradation of a PMOS transistor based on it. After deriving the above delay degradation, we take into account the circuit structure to estimate the longterm delay degradation of the whole system.…”

Section: The Proposed Simulation Frame-workmentioning

confidence: 99%

“…In our experiment, the high voltage corresponds to V dd , the low voltage corresponds to 0.8V dd . We use the same DVFS strategy as from [15]: when the highest/lowest temperature of the processor is higher/lower than the threshold temperature TH /TL, it decreases/increases its supply voltage or frequency. We assume the transition time between states is zero and set TH = 353.15K and TL = 343.15K.…”

Section: The Impact Of Dvfsmentioning

confidence: 99%

“…However, it is impossible to simulate the entire service life of a system with various types of workloads. To mitigate this problem, in [15], the authors proposed a novel simulation framework, namely AgeSim, to estimate system lifetime by running representative workloads only (see Fig. 1).…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…The high-level lifetime reliability models presented in [15], however, cannot be used for analyzing NBTI-induced performance degradation, because of the following reasons: (a) NBTIinduced degradation is not additive along time axis [8], and therefore accumulating individual degradation from separate time units leads to inaccurate estimation of the long-term degradation; (b) The state-related scale parameter Θ(Ti, Si) is difficult to calculate for individual devices, like PMOS transistor, and therefore is only applicable for statistical analysis of failure mechanisms, in which scale parameter has a simple relation with Mean-Time-To-Failure under the assumption of Weibull distribution; (c) AgeSim does not take circuit structure into consideration, while NBTI effects are strongly related to circuit structure as they would only affect critical paths or near-critical paths, denoted as potential critical paths (PCPs) in this paper. Motivated by the above, in this work, we present a comprehensive analytical model and the corresponding simulation framework for NBTI-induced performance degradation.…”

Section: Related Work and Motivationmentioning

confidence: 99%

See 2 more Smart Citations

On the simulation of NBTI-Induced performance degradation considering arbitrary temperature and voltage variations

Wang

2014

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

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Dependability Threats

Bolchini¹,

Michael²,

Miele³

et al. 2017

Dependable Multicore Architectures at Nanoscale

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The increasing diversity, density, and complexity of electronic devices is enabling the so-called digital revolution with the evident pervasive presence of electronics in everybody's lives. The benefits of this ubiquitous presence are impressive and widespread: from the constant improvement of productivity in the workplace to the societal impact of a constantly connected and sharing community.Whatever is the considered scenario, all this incredible progress has been relying on the assumption that the devices can be depended on in their application and for their purposes. The foundations for this assumption are based on a constant work behind the scenes of the technical and scientific community aimed at enhancing the dependability of the devices.Dependability is a broad term that summarizes several aspects of a system, which typically include availability, reliability, maintainability, safety, and security. All these aspects define whether and how the system will behave according to several requirements which can have different levels of priority based on the specific application. In particular, availability measures the amount of time a system is readily operating, reliability measures the continuity of the correct service, maintainability shows the ability of the system of being repaired and/or modified, safety targets the avoidance of catastrophic consequences in the case of lack of service, and finally security targets the resilience of a systems to threats caused by malicious third parties.There is an impressive amount of examples from technical literature and from the news about the dreadful consequences of the lack of dependability of an electronic system. Lack of dependability may have several negative consequences spreading from the loss of reputation of a manufacturer to the catastrophic loss of lives. Consider for example the automotive scenario, several cases of massive recalls were caused by issues in the electronic system: famously in one of such cases it was speculated that unintended acceleration causing loss of lives was to be ascribed to faults occurring in the drive-by-wire control modules.Apart from the loss of lives, the economic impact of unreliable hardware must also be taken into account. Depending on the particular product and application domain, the costs associated to lack of dependability can be extremely high:xiii

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AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs

Abstract: ABSTRACT

Cited by 20 publications

References 22 publications

Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems

Reliability-Driven Task Mapping for Lifetime Extension of Networks-on-Chip Based Multiprocessor Systems

On the simulation of NBTI-Induced performance degradation considering arbitrary temperature and voltage variations

Dependability Threats

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