Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application

Fujii, Shosuke; Ichihara, Reika; Konno, Tomohiro; Yamaguchi, Mari; Seki, Harumi; Tanaka, Hiroki; Zhao, Dongfeng; Yoshimura, Y.; Saitoh, Masumi; Koyama, Masato

doi:10.23919/vlsit.2019.8776568

Cited by 9 publications

(4 citation statements)

References 1 publication

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“…The size of the device being integrated in a billion scaled VLSI chip is continuously scaled down to a sub-10-nano meter region [1][2]. And thanks to this technology advancement, the total bit density in the VLSI chip has increased up to a Tera-bit scale [3].…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we assumed that the random variables that have such pdf are the values for the six threshold voltages (Vth) for the six MOSFET devices that make up the 1bit cell for the 6Tstatic random access memory (SRAM). Those variations for the random variables are mainly caused by the atomic scaled ion-implantation dose fluctuation and gate-oxide electron trap/de-trap phenomena [4][5][6][7][8][9][10][11] and divided into the two random variations caused by (1) the Random Spatial Variation (RSV) and (2) the Random Temporal Variation (RTV). As a result, the tail length of the minimum operating voltage (VDDMIN) pdf distribution of the SRAM has become spatially and temporally longer [12] because both variations of the RSV and the RTV become larger.…”

Section: Introductionmentioning

confidence: 99%

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A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

Yamauchi

Somha

2023

J. Phys.: Conf. Ser.

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A Richardson-Lucy algorithm (RLA) based blind deconvolution with a new filter design technique was successfully developed. This allowed decoupling and retrieving of the information of the two unknown factors at once for the Random Temporal Variation (RTV) and the Random Spatial Variation (RSV). The variations of SRAM operating voltage (VDDMIN) are caused by the two coupled factors of RTV and RSV. Thus, this decoupling technique is prerequisite for the margin analysis. The designs of the device characteristics and the screening test conditions based on the analysis results were briefly demonstrated. The proposed filter design technique for the RLA based blind deconvolution allowed to circumvent the ill-conditioning ringing phenomena. This gives to enjoy the advantage in convergence speed and simplicity of the RLA. The relative errors of the blind-deconvolution for the RSV and RTV distributions were reduced to less than 0.3% within only 300-iteration cycles compared with the conventional one.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

Yamauchi

Somha

2023

J. Phys.: Conf. Ser.

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“…The authors are with the Department of Electrical and Information Technology, Lund University, SE-221 00 Lund, Sweden. M. Borg is also with NanoLund, Lund University 22100 Lund, Sweden (e-mail: saketh_ram.mamidala@eit.lth.se) demonstrated to be promising, using a III-V selector would allow to scale the supply voltage for a constant programming and read-out current while simultaneously suppressing leakage currents [10][11][12]. An optimized III-V VNWFET reported in Kilpi et.…”

Section: Introduction Euromorphic Andmentioning

confidence: 99%

Low-Power Resistive Memory Integrated on III–V Vertical Nanowire MOSFETs on Silicon

Ram

Persson

Borg

et al. 2020

IEEE Electron Device Lett.

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III-V vertical nanowire MOSFETs (VNW-FETs) have the potential to extend Moore's law owing to their excellent material properties. To integrate highly scaled memory cells coupled with high performance selectors at minimal memory cell area, it is attractive to integrate low-power resistive random access memory (RRAM) cells directly on to III-V VNW-FETs. In this work, we report the experimental demonstration of successful RRAM integration with III-V VNW-FETs. The combined use of VNW-FET drain metal electrode and the RRAM bottom electrode reduces the process complexity and maintains material compatibility. The vertical nanowire geometry allows the RRAM cell area to be aggressively scaled down to 0.01 µm 2 enabling realization of dense memory (1T1R) cross-point arrays on silicon.

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“…Emerging memories such as magnetic random access memory, [1][2][3][4][5] resistive random access memory, [6][7][8][9][10][11][12] ferroelectric random access memory, [13][14][15][16] phase change memory, [17][18][19][20][21][22] and ionic memory [23][24][25] are receiving much attention due to their non-volatility, simple structure, scalability, low power consumption, and high-speed operation. Also, emerging memories are expected to be used for various applications such as storage-class memories, [26][27][28][29][30] embedded memories for microcontrollers unit, 31,32) system on a chip, 32,33) and in-memory computing 34,35) for neuromorphic applications.…”

Section: Introductionmentioning

confidence: 99%

A high-precision 1 Ω–10 MΩ range resistance measurement platform for statistical evaluation of emerging memory materials

Maeda¹,

Omura²,

Kuroda³

et al. 2020

Jpn. J. Appl. Phys.

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We developed an accuracy improved resistance measurement platform for statistical evaluation of emerging memory materials. The developed platform excludes on-resistance of selectors (R ON ), resulting in high measurement accuracy with a measurement error of 10% or less across the measurement range of 1 Ω-10 MΩ. The developed platform can accurately measure the resistance of various memory materials on a large scale of 360 000 cells within 50 ms. Various memory materials can be tested only by forming them on top of the platform. The circuit operation was verified, and the effect of R ON exclusion was confirmed using 6000 Poly-Si cells.

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Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application

Cited by 9 publications

References 1 publication

A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

A Richardson-Lucy Algorithm Based Blind Deconvolution to Decouple the Two Unknown Spatial-Temporal SRAM Margin Variations

Low-Power Resistive Memory Integrated on III–V Vertical Nanowire MOSFETs on Silicon

A high-precision 1 Ω–10 MΩ range resistance measurement platform for statistical evaluation of emerging memory materials

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