Advances in RF packaging technologies for next-generation wireless communications applications [RFIC]

Larson, L.E.; Jessie, D.

doi:10.1109/cicc.2003.1249412

Cited by 15 publications

(10 citation statements)

References 23 publications

(11 reference statements)

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“…Theoretical electrical models for wire bonds and for device packages have been proposed in the literature with different level of accuracy depending on the application [3], [8][9]. In this work , a lumped resistance-inductor-capacitor (RpLpCp) parasitic model was adopted for wire bond and for package pins , but it will be represented by a parasitic inductor (L p = L H W + L u ) for clearness ( Fig.…”

Section: A Conventional Fast Gate-drivermentioning

confidence: 99%

“…When switching off the supply current, the fast current variation produces an internal supply voltage overshoot due to the parasitic inductances inbuilt in bond wires, L BW, and in package pins, LLF, on the serial path connected with the switches [3]. Although the low values of these parasitic inductances when compared with the external inductor of the buck converter, L, their effects can not be neglected when using high switching frequency and high current since they are the main reasons for spikes on internal supply voltage, VIN. These spikes can cause overvoltage that leads to device destruction, reliability problems or malfunctions on the converter feedback control [1], [4][5].…”

Section: Introductionmentioning

confidence: 99%

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Limiting internal supply voltage spikes in DC-DC converters

Rocha

Santos

Santos³

et al. 2009

2009 IEEE International Symposium on Industrial Electronics

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Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

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Section: A Conventional Fast Gate-drivermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Limiting internal supply voltage spikes in DC-DC converters

Rocha

Santos

Santos³

et al. 2009

2009 IEEE International Symposium on Industrial Electronics

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“…Most of the papers written on LTCC packaging are on the field of RF modules [3][4][5]. The integration of RF circuits and high-speed circuits, passive alignment structures, thermal management structures as well as hermetic encapsulation into the LTCC platform are relevant, when considering the capabilities of LTCC system-on-package (SOP) for the hybrid integration of high-speed electronics, RF circuits and photonics.…”

Section: Introductionmentioning

confidence: 99%

LTCC Technology for Photonic and Millimeter Wave Module Integration

Keränen

Karppinen

Lenkkeri

et al. 2005

Int. J. Soft. Eng. Knowl. Eng.

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In the module integration process, lower level packaging elements such as devices, sub-mounts and components are combined as a functional block. Embedded sub-system consists of modules whose operations are controlled by a specific algorithm. Typically, the control algorithm is realized in a form of system software in a processor unit, which controls individual module operations and combines separate module operations as a system operation. In the creation of a cost-efficient embedded system it is essential that reliable, reproducible and cost-efficient building blocks of systems, modules, can be manufactured. We have studied Low Temperature Co-fired Ceramics (LTCC) substrate technology and its possibilities to produce reliable, reproducible and cost-efficient photonic and millimeter wave modules.In this paper we introduce our contribution to the development of LTCC photonic and millimeter wave modules. Most of the papers written on LTCC packaging are in the field of RF and millimeter wave modules and are shortly reviewed in this paper. Photonic modules utilizing LTCC substrates are almost missing in the literature. Several photonic modules based on the use of LTCC substrates developed by our group are introduced in this paper, including hermetic fiber pigtailed power laser, wavelength tunable laser and 10 GBit/s/ch optical interconnects board for photonic applications. In addition, front-end module for 24 GHz transceiver for millimeter wave applications is introduced.

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“…As an example, packaging of RF silicon ICs with simultaneous integration of high-quality passives, antennas or isolation structures [1] or protection of MEMS structures [2] can be mentioned. The emerging WLCSP technology and related integrated passive devices (IPDs) have proven to have capabilities of significant size reduction at a comparable cost and an improved electrical performance [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Influence of via-connections on electrical performance of vertically-spaced RF passives

Bartek

Sinaga

Burghartz

Proceedings Electronic Components and Technology, 2005. ECTC '05.

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Electrical performance of via-connected rectangular spiral inductors integrated on a low-loss spacer substrate and thus vertically-spaced above a lossy silicon substrate is analyzed using 3D electromagnetic simulation tool Ansoft HFSS with a goal to identify the optimum via-interconnect scheme. The results show that vertically spaced spiral inductors with a properly designed via-interconnect scheme is a viable option to achieve high-quality passives and to minimize chip area of silicon RF ICs. Improperly designed electrical via interconnect can severely degrade electrical performance of spiral inductors due to the in-via induced eddy currents and/or parasitic capacitances. Smaller via diameters and their larger separations are preferable to minimize parasitic capacitances. The optimum via length (i.e. spacer substrate thickness) is in the range of 100-200 µm, when the influences of a lossy silicon substrate and via capacitances are minimized. IntroductionAs the demand for ever-smaller electronic systems grows, manufacturers are seeking ways to increase IC integration levels and to reduce the size and weight of IC packages. The explosive expansion of mobile electronic terminals generates strong demand for high-performance, cost-effective and miniaturized RF modules providing desired wireless connectivity. Ideally, they should be realized as a single-chip solution and could easily be embedded into any electronic system. Such System-on-Chip (SoC) RF ICs have set a challenge for packaging, especially at the low-end market segment where low-cost solutions are required. The chip size package (CSP) and wafer-level packaging (WLP) resulting from this effort, have been introduced into manufacturing at an unprecedented rate.The driving force behind is not only the reduced size and weight, but primarily the fact that the wafer-level chip-scale packaging (WLCSP) technology has potential of electrical performance improvement at a comparable or even reduced manufacturing cost and thus providing an improved performance-to-price ratio. Moreover, the same processing steps that are used to achieve the WLP technology basic packaging goal can be adopted for implementation of an additional functionality at no or very limited additional cost. As an example, packaging of RF silicon ICs with simultaneous integration of high-quality passives, antennas or isolation structures [1] or protection of MEMS structures [2] can be mentioned. The emerging WLCSP technology and related integrated passive devices (IPDs) have proven to have capabilities of significant size reduction at a comparable cost and an improved electrical performance [3], [4].

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Advances in RF packaging technologies for next-generation wireless communications applications [RFIC]

Cited by 15 publications

References 23 publications

Limiting internal supply voltage spikes in DC-DC converters

Limiting internal supply voltage spikes in DC-DC converters

LTCC Technology for Photonic and Millimeter Wave Module Integration

Influence of via-connections on electrical performance of vertically-spaced RF passives

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