Limiting internal supply voltage spikes in DC-DC converters

Abstract

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35 mu m CMOS technology.

Analysis of a monolithic buck converter's pMOS switch during turn off

“…Fig. 2 shows a simplified version of the circuit waveforms, shaped only by piecewise linear sections [3][4][5]. The analysis can be divided in four time frames: before the first time frame, M P is fully conducting in the triode region, and its current is increasing at an approximately linear rate given by (V PVINIv OUT )/L with a maximum value of I L , (i L ) max =I L , and i 1 ≈ i P ≈ I L .…”

“…However, until now, these gate divers are designed with minimal theoretical support of the behavior of M P during its on-to-off commutation. This commutation is analyzed in this work, under the presence of parasitic impedances in the power supply path, giving theoretical background to understand HSpice results described in previous communications [2][3][4]. This paper has four more sections.…”

“…This path has parasitic inductances inbuilt in package pins and bond wires and, when they are troughed by fast current variations, voltage spikes are produced in internal supply nodes (PVINI and PGNDI of fig. 1) [2][3][4][5]. These spikes can be hazard to the chip because the overvoltage can affect its reliability or lead to its destruction, when commuting a high current at high switching frequency.…”

“…The reduction of the magnitude of the voltage spike requires a lower parasitic inductance or a smaller current time derivative [2][3][4], and this derivative is asserted by M P during its turning-off commutation. Some authors describe gate drivers of the M P switch, that implement a smart time derivative control, which limits the voltage spike magnitude without excessive turn-off time duration, leading to an increase of power efficiency [3][4].…”

“…Some authors describe gate drivers of the M P switch, that implement a smart time derivative control, which limits the voltage spike magnitude without excessive turn-off time duration, leading to an increase of power efficiency [3][4]. However, until now, these gate divers are designed with minimal theoretical support of the behavior of M P during its on-to-off commutation.…”