Advanced source/drain technologies for parasitic resistance reduction

Abstract

To achieve high MOSFET drive current and speed in future technology nodes, potential bottlenecks such as high contact resistance should be resolved. In this paper, we review the technology solutions available for reducing the contact resistance between a metal silicide contact and the source/drain region. Novel approaches for reducing the electron and hole barrier heights between the metal silicide contact and the source/drain region in n-and p-FETs will be examined. Integration of these approaches in advanced device architectures will be shown.

Device scaling and performance improvement: Advances in ion implantation and annealing technologies as enabling drivers

“…Yeo et at investigated si licide film resistivities and SBH values for various silicides types. For NiSi SBH is reduced by incorporating a high concentration of dopant at the interface between NiSi and silicon and/or by incorporating into the interface region exotic species such as AI, Se, S [8,9]. Figures 8 and 9 indicate that there is an opportunity for significant SBH reduction in NMOS by implantation of aluminum into the NiSi/nSi interface region.…”

“…Electron barrier height C(:>Bn versus film resistivity for various contact silicides formed on silicon. The labels "As +", "S+" and "Se +" refer to samples in which arsenic, sulphur and selenium were implanted prior to silicidation [9]. Overall, as device pitch continues its O.7X node-to-node scaling beyond sub-20nm nodes, the impact of contact resistance scaling is expected to become only more severe regardless of whether the industry stays with a planar device architecture or is transitioning to FinFET devices.…”