Proceedings of the 19th International Symposium on Power Semiconductor Devices and IC's 2007
DOI: 10.1109/ispsd.2007.4294948
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Advanced Power SiP with Wireless Bonding for Voltage Regulators

Abstract: An advanced power system in package (SiP) for voltage regulators is presented; it offers the world's lowest power dissipation of 4.4 W at 1 MHz, with an output voltage of 1.3 V and an output current of 25 A. Its package resistance is 88% lower due to using Cu leads for the bonding, which reduces the spreading resistance of the MOSFET. The diode loss is 43% lower due to using a Schottky barrier diode incorporated into the low-side MOSFET. The thermal resistance is also 43% lower due to using a large topside Cu … Show more

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Cited by 17 publications
(3 citation statements)
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“…For example, in the previous works, a Cu lead technology, the multi-chip module and the power module technologies achieved high speed and low noise switching characteristics by the reduction of the stray inductance. [24][25][26] In the future, for discrete power devices, the lead inductance in the package cannot be neglected. To avoid the self-turn-on operation, the gate surge voltage induced by the parasitic inductance must be suppressed less than the gate threshold voltage V th .…”
Section: Discussionmentioning
confidence: 99%
“…For example, in the previous works, a Cu lead technology, the multi-chip module and the power module technologies achieved high speed and low noise switching characteristics by the reduction of the stray inductance. [24][25][26] In the future, for discrete power devices, the lead inductance in the package cannot be neglected. To avoid the self-turn-on operation, the gate surge voltage induced by the parasitic inductance must be suppressed less than the gate threshold voltage V th .…”
Section: Discussionmentioning
confidence: 99%
“…Thermal control is one most critical issue for both operating performance and long-term reliability thereof. To improve the packaging thermal efficiency, packages such as D2PAK, D-PAK, Power SOP and MLP are broadly accepted approaches [5][6][7][8]. In these packages, heat generated at the face of the die has to travel through the bulk of the silicon and through the heat sink to be finally dissipated through the printed circuit board and the ambient.…”
Section: Technology Analysismentioning
confidence: 99%
“…Future MCM developments aim at continuing the reduction of the parasitic elements, in particular, the half-bridge loop inductance [221]- [224], adding further power saving functionality, such as the control modes for light load described in section 1.2.7.3, and implement advanced packaging with, for instance, embedded technologies [225], [226].…”
Section: Packaging and Integrationmentioning
confidence: 99%