Advanced low voltage single chip radio IC

Okanobu, T.; Tomiyama, Hiroyuki; Arimoto, Hideki

doi:10.1109/30.156724

“…In practice, the precision 90º phase is hard to achieve due to the mixers, mismatching, thus the rejection will be around 30-40 dB [15,18]. The image rejection ratio is (IRR) is defined as Eq.…”

Section: Image Reject Receivermentioning

confidence: 99%

CMOS Low Noise Amplifiers for Wireless Body Area Networks Applications: Techniques and Designs

Rezvani¹

2021

Preprint

0

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Recently, the growing advances in communication systems has led to urgent demand for low power, low cost, and highly integrated circuit topologies for transceiver designs, as key components of nearly every wireless application. Regarding to the usually weak input signal of such systems, the primary purpose of the wireless transceivers is consequently amplifying the signal without adding additional noise as much as possible. As a result, the performance of the low noise amplifier (LNA), measured in terms of features like gain, noise figure, dynamic range, return loss and stability, can highly determine the system’s achievement. Along with the evolution in wireless technologies, people get closer to the global seamless communication, which means people can unlimitedly communicates with each other under any circumstances. This achievement, as a result, paves the way for realizing wireless body area network (WBAN), the required applications for wireless sensor network, healthcare technology, and continuous health monitoring. This thesis suggests a number of LNA designs that can meet a wide range of requirements viz gain, noise figure, impedance matching, and power dissipation at 2.4Ghz frequency based on 0.13μm and 65nm CMOS technologies. This dissertation focused on the low power, high gain, CMOS reused current (CICR) LNA with noise optimization for on-body wireless body area networks (WBAN). A new design methodology is introduced for optimization of the LNA to attain gain and noise match concurrently. The designed LNA achieves a 28.5 dB gain, 2.4 dB noise figure, -18 dB impedance matching, while dissipating 1mW from a 1.2V power supply at 2.4 GHz frequency which is intended for WBAN applications. The tests and simulations of LNA are utilized in Cadence IC6.15 with IBM 130nm CMRF-8-SF library. The provided CICR LNA results inclusively prove the advantages of our design over other recorded structures. In the second step, a new linearization method is proposed based on Cascade LNA structure (CC-LNA). The proposed negative feedback intermodulation sink (NF-IMS) method benefits from the feedback to improve the linearity of CC-LNA. It proves that the additional negative feedback enhances the linearity of LNA despite the previous research. Furthermore, the heavily mathematical calculations of NF-IMS technique are carried on with the proposed modified Volterra series method. The NF-IMS method demonstrates more than 9.5dBm improvement in IIP3. Comparing to the previous techniques like: MDS and IMS, the improvement in the linearity aspect of the CC-LNA with is significant while it achieves a sufficient gain and noise performance of 16.7dB and 1.26db, respectively. Besides, the NF-IMS method presents a noise cancellation behavior as well. To increase the practical reliability of simulation, the real element model from TSMC 65nm CRN65GP library is applied. The CC-LNA that employed NF-IMS method is an excellent match with the market demands in WBAN’s gateway applications.

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“…In practice, the precision 90º phase is hard to achieve due to the mixers, mismatching, thus the rejection will be around 30-40 dB [15,18]. The image rejection ratio is (IRR) is defined as Eq.…”

Section: Image Reject Receivermentioning

confidence: 99%

CMOS Low Noise Amplifiers for Wireless Body Area Networks Applications: Techniques and Designs

Rezvani¹

2021

Preprint

0

View full text Add to dashboard Cite

Recently, the growing advances in communication systems has led to urgent demand for low power, low cost, and highly integrated circuit topologies for transceiver designs, as key components of nearly every wireless application. Regarding to the usually weak input signal of such systems, the primary purpose of the wireless transceivers is consequently amplifying the signal without adding additional noise as much as possible. As a result, the performance of the low noise amplifier (LNA), measured in terms of features like gain, noise figure, dynamic range, return loss and stability, can highly determine the system’s achievement. Along with the evolution in wireless technologies, people get closer to the global seamless communication, which means people can unlimitedly communicates with each other under any circumstances. This achievement, as a result, paves the way for realizing wireless body area network (WBAN), the required applications for wireless sensor network, healthcare technology, and continuous health monitoring. This thesis suggests a number of LNA designs that can meet a wide range of requirements viz gain, noise figure, impedance matching, and power dissipation at 2.4Ghz frequency based on 0.13μm and 65nm CMOS technologies. This dissertation focused on the low power, high gain, CMOS reused current (CICR) LNA with noise optimization for on-body wireless body area networks (WBAN). A new design methodology is introduced for optimization of the LNA to attain gain and noise match concurrently. The designed LNA achieves a 28.5 dB gain, 2.4 dB noise figure, -18 dB impedance matching, while dissipating 1mW from a 1.2V power supply at 2.4 GHz frequency which is intended for WBAN applications. The tests and simulations of LNA are utilized in Cadence IC6.15 with IBM 130nm CMRF-8-SF library. The provided CICR LNA results inclusively prove the advantages of our design over other recorded structures. In the second step, a new linearization method is proposed based on Cascade LNA structure (CC-LNA). The proposed negative feedback intermodulation sink (NF-IMS) method benefits from the feedback to improve the linearity of CC-LNA. It proves that the additional negative feedback enhances the linearity of LNA despite the previous research. Furthermore, the heavily mathematical calculations of NF-IMS technique are carried on with the proposed modified Volterra series method. The NF-IMS method demonstrates more than 9.5dBm improvement in IIP3. Comparing to the previous techniques like: MDS and IMS, the improvement in the linearity aspect of the CC-LNA with is significant while it achieves a sufficient gain and noise performance of 16.7dB and 1.26db, respectively. Besides, the NF-IMS method presents a noise cancellation behavior as well. To increase the practical reliability of simulation, the real element model from TSMC 65nm CRN65GP library is applied. The CC-LNA that employed NF-IMS method is an excellent match with the market demands in WBAN’s gateway applications.

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“…Many efforts have been made to integrate an FM receiver on a single chip using various architectures, but the performance has been limited by the analog signal-processing accuracy [6][7][8]. The main issue of integrating an FM demodulator on a chip is how to accurately discriminate a small frequency deviation of the FM signal from its center frequency.…”

Section: Related Workmentioning

confidence: 99%

Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop

Brito

¹

,

Bampi

²

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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A software-defined radio (SDR) is a wireless communication device in which all of the signal processing is implemented in software. By simply downloading a new program, a SDR is able to interoperate with different wireless protocols, incorporate new services, and upgrade to new standards. Therefore, FPGAs have been used extensively for implementing essential functions in SDR architectures. In this paper, we explore the design of a Digital FM Receiver using the approach of an All-Digital Phase Locked-Loop (ADPLL). The digital FM Receiver circuit is designed using pure VHDL, then simulated and synthesized using ModelSim SE 6 and LeonardoSpectrum Level 3, respectively. The final circuit operates at a frequency up to 150MHz and occupies the area around 15K logic gates.

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Advanced low voltage single chip radio IC

Cited by 28 publications

References 2 publications

CMOS Low Noise Amplifiers for Wireless Body Area Networks Applications: Techniques and Designs

CMOS Low Noise Amplifiers for Wireless Body Area Networks Applications: Techniques and Designs

CMOS Low Noise Amplifiers for Wireless Body Area Networks Applications: Techniques and Designs

Design of a digital FM demodulator based on a 2nd° order all-digital phase-locked loop

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