Advanced low power RISC processor design using MIPS instruction set

Abstract

Present era of SOC's comprise analog, digital and mixed signal components housing on the same chip. In this environment processor plays a vital role. As the technology shrinking to sub-micrometer technology node, there exists a huge scope of undesirable hazards in processors. These hazards may lead to disturbance in area, power and timing which deviate from desired quantities. Our paper focuses mainly to solve some of these issues. In-order to tackle these problems, we are introducing the enhanced version of MIPS. Microprocessor without Interlocked Pipeline Stages (MIPS) is a recent architecture into the semi-conductor industry. This paper totally concentrates on designing the architecture in Verilog HDL. The design had been simulated and synthesized in Nc-launch and RTL-compiler licensed by cadence Inc respectively. The physical design of synthesized architecture had been carried on by Socencounter under slow.lib library of TSMC Cmos 180nm technology node. . Keywords-Hazard Detection Units , Low Power Processor , MIPS, RISC using MIPS1. Register Type (R-Type)

Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

“…The advantage of SDRAM over existing memories is its lower power consumption, lower cost, higher speed and allocation of high volume. High performance DDR4 SDRAM based controller [8] is used in this pipeline design to bridge the connectivity between SDRAM memory devices and processors subsystem 2) Auxilary components a) Low Power Unit:…”

“…But conventional RISC processor is always busy with their reduced Instruction set, which leads to system delay. Hence, MIPS (Microprocessor without Interlocked Pipelining Stages) became a better alternative to it by exploiting all the advantages of conventional RISC [8]. Any processor when executes millions of instructions per second, a concern arises called "interlocking in the pipeline stages"; and the solution is MIPS, which will take care of such issues.…”

A Comprehensive Analysis on Data Hazard for RISC32 5-Stage Pipeline Processor

“…The pipeline hazards can be classified into 3 types, structural hazard, control hazard and data hazard [1], [3], [6]. Data hazards always exist in a processor designed based on pipeline approach.…”

“…The software approach relies on compiler to reorder the user code or insert a delay slot to resolve the combinations of instructions that might produce data hazard, which highly depends on the robustness of the compiler technology. Resolving data hazard using software approach is less complex but will affect the processor throughput more severely than the hardware approach [6]. Consider a case of an adding of two values in registers, $t1 and $t2, the result will be store to register $t0.…”