2010 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) 2010
DOI: 10.1109/csics.2010.5619667
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Advanced Heterogeneous Integration of InP HBT and CMOS Si Technologies

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Cited by 21 publications
(8 citation statements)
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“…The interaction of the probe with the surrounding structures is clearly visible. The impact of this coupling and excitation of parasitic modes on the calibration procedure can be evaluated, when simulating different calibration standards in microstrip technology [4] and CPW environment [1], [2], [5], [6], respectively. As an example, Fig.…”
Section: Pitfalls In On-wafer Calibration At Mm-wave Frequenciesmentioning
confidence: 99%
See 1 more Smart Citation
“…The interaction of the probe with the surrounding structures is clearly visible. The impact of this coupling and excitation of parasitic modes on the calibration procedure can be evaluated, when simulating different calibration standards in microstrip technology [4] and CPW environment [1], [2], [5], [6], respectively. As an example, Fig.…”
Section: Pitfalls In On-wafer Calibration At Mm-wave Frequenciesmentioning
confidence: 99%
“…COSMOS [5], [6], or SciFab [7]- [10]. The major driving force is to provide high-speed III-V semiconductor devices on Si platforms, providing not only speed improvement without trade-off in signal amplitude, but also functional complexity to high-speed circuits.…”
Section: Heterogeneous Mmic Device Testingmentioning
confidence: 99%
“…The heterogeneous integration of III-V devices and complementary metal oxide semiconductor (CMOS) processes has been explored in the area of power electronics in recent years [19][20][21]. For instance, the Defense Advanced Research Projects Agency (DARPA) Diverse Accessible Heterogeneous Integration (DAHI) program has demonstrated InP chips integrated on CMOS chips through flip-chip bonding [22][23][24]. The direct integration of III-V devices on top of CMOS wafers has been shown to achieve better function complexities [25] as well as a reduction in board space required over conventional monolithic designs [26,27].…”
Section: Introductionmentioning
confidence: 99%
“…In recent years, several approaches to integrating InP transistors with CMOS have been pursued, ranging from InP/silicon heteroepitaxy () to adhesive and oxide () wafer‐ and die‐bond integration. In this paper, we present advances in the heterogeneous integration processing which resulted in the realization of a robust and reproducible InP DHBT/SiGe BiCMOS‐heterointegrated technology, enabling first‐pass design of complex integrated RF mm‐wave and sub‐mm‐wave front ends.…”
Section: Introductionmentioning
confidence: 99%