Advanced Electron Microscopy for III/V on Silicon Integration

Abstract

The combination of III/V semiconductors with Si is very attractive, since it allows the fabrication of high efficient optoelectronic devices like solar cells, lasers or the integration of III/V transistors on Si substrates. However, the growth of polar III/V materials on nonpolar Si holds several challenges. The different valences of group III and group V atoms as well as Si possibly give rise to the formation of charged defects, i.e., antiphase boundaries, as well as to charge accumulation at the interface between the different materials. Accordingly, the interfaces present, i.e., the ones between antiphase and main phase and the one between III/V and Si, eventually limit any device's performance. Electron microscopy, in particular transmission electron microscopy, has proven to be a valuable tool to acquire quantitative information from III/V–Si heterostructures. Among this information are defect densities as well as the structure of the involved interfaces at spatial resolutions down to the atomic level. Moreover, information on charge distribution can be retrieved. In this review, the authors collocate the results gained for the model system GaP on Si utilizing various electron microscopy related techniques.

Inversion Boundary Annihilation in GaAs Monolithically Grown on On‐Axis Silicon (001)

“…As shown in the dark‐field TEM image of Figure 5a, the IBs nucleate through the (110) plane in Sample B in the LT GaAs layer. Subsequently, the IBs start to propagate along a higher index plane, such as {111}, {112} and {113} planes, [ 30 ] through the MT and HT GaAs layers. This enhances the probability of IBs’ intersecting and annihilating with each other.…”

“…The visible deep trenches on the SEM image illustrate the location of IBs since material evaporate easier on IBs due to week bonding than normal III-V crystal. [30,34] Therefore, we further optimized the growth method by employing a three-step 1 µm GaAs growth for Sample B, a 250 nm GaAs nucleation layer was first grown at a low temperature (LT) of 350 °C on the deoxidized Si (001) substrate, followed by a deposition of another 250 nm GaAs layer at a mid-temperature (MT) of 420 °C. Finally, a 500 nm GaAs layer was grown at a high temperature (HT) of 580 °C to finish the growth.…”

“…However, these methods require hydrogen gas and Si substrates with intentionally selected offcut angles (0.15° and 0.12° for the growth of GaAs/Si and GaP/Si respectively) to promote the formation of dominated D steps while few S islands remain at the step edge. [26,[28][29][30] IBs that only arise from these few S islands remain low density and intersect pairwise during the subsequent high temperature layer growth, leading to sufficient IBs selfannihilation. Those methods are incompatible with solid-source molecular beam epitaxy (MBE) growth, due to lack of hydrogen source.…”

State of the Art and Future Perspectives in Advanced CMOS Technology

“…APDs will eventually result in unexpected nonradiative recombination surfaces and deterioration of the devices performance. Compared with single element materials, the first challenge that III-V compound semiconductors need to overcome in heteroepitaxy is antiphase boundaries (APDs) [313,314]. Taking Figure 45 as an illustration, GaAs is grown on Ge with incomplete pre-layer coverage and several odd-atom steps are introduced in the surface during the process of material growth.…”

Characterization of III/V Semiconductors on Silicon by Analyzing 4D-STEM Data with Convolutional Neural Networks

“…Growing III/V compounds on Si is challenging, e.g. due to the formation of charges at interfaces and antiphase defects [1]. Hence characterization on the nanoscale is crucial.…”