Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate

Ansari, Mohammad; Kotselidis, Christos; Jarvis, Kim; Luján, Mikel; Kirkham, Chris; Watson, Ian

doi:10.1007/978-3-540-85451-7_77

Cited by 37 publications

(45 citation statements)

References 7 publications

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“…Throttle for yada). Meanwhile, we notice in some benchmarks (kmeans-low) that enabling ACCs could reduce speedup or scalability even for ITC within normal range (2)(3)(4)(5)(6)(7)(8). Although some programs get slowdown from ACCs enabled, ACCs show positive effect from an average point of view.…”

Section: Resultsmentioning

confidence: 99%

“…Ansari et al [5] proposed control mechanisms to adjust active thread count according to the so-called transaction commit rate (TCR) which we would regard as commit ratio. They tested only with sparingly few applications to show the effectiveness.…”

Section: Related Workmentioning

confidence: 99%

“…On the other hand, if the thread scheduler observes that the present execution seldom encounters conflicts, it may speculate on boosting concurrency on-the-fly for better speedup. We see that research efforts [5,6,7,8] in a similar direction yet nascent condition have lately begun (Section 5). To advance the state of the art, the contributions of this paper are two-fold:…”

Section: Introductionmentioning

confidence: 97%

See 2 more Smart Citations

Adaptive Thread Scheduling Techniques for Improving Scalability of Software Transactional Memory

Chan¹,

Lam²,

Wang³

2011

Parallel and Distributed Computing and Networks / 720: Software Engineering

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Software transactional memory (STM) enhances both ease-of-use and concurrency, and is considered state-ofthe-art for parallel applications to scale on modern multicore hardware. However, there are certain situations where STM performs even worse than traditional locks. Upon hotspots where most threads contend over a few pieces of shared data, going transactional will result in excessive conflicts and aborts that adversely degrade performance. We present a new design of adaptive thread scheduler that manages concurrency when the system is about entering and leaving hotspots. The scheduler controls the number of threads spawning new transactions according to the live commit throughput. We implemented two feedback-control policies called Throttle and Probe to realize this adaptive scheduling. Performance evaluation with the STAMP benchmarks shows that enabling Throttle and Probe obtain best-case speedups of 87.5% and 108.7% respectively.

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Section: Resultsmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 97%

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Adaptive Thread Scheduling Techniques for Improving Scalability of Software Transactional Memory

Chan¹,

Lam²,

Wang³

2011

Parallel and Distributed Computing and Networks / 720: Software Engineering

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“…Our earlier work [31,19] on dynamically adapting to available parallelism in an STM application, by changing the number of threads permitted to execute transactions (in a thread pool), reduced the number of aborts, and reduced wasted work. Yoo and Lee [32] implemented a STM transaction scheduling framework that queues threads onto a global queue if they greater than a user-specified threshold of aborts over a history window of transactions, which resulted in similar functionality to our adaptive work, although our solution has the ability to be more responsive in certain cases.…”

Section: Related Workmentioning

confidence: 99%

“…STMs remove this limitation, but at the cost of increased conflict detection overhead. Research in TM has focused on reducing the overhead of conflict detection, but also on understanding TM behavior [18], and even on adapting to dynamic workload characteristics [19,20]. This paper focuses on HTMs.…”

mentioning

confidence: 99%

Improving Performance by Reducing Aborts in Hardware Transactional Memory

Ansari

Khan

Luján

et al. 2010

High Performance Embedded Architectures and Compilers

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Abstract. The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, and may lead to aborts that increase wasted work, and degrade performance. A promising approach to reducing conflicts at runtime is dynamically, and transparently, reordering the execution of transactions upon discovery of conflicts. This approach has been explored in Software TMs (STMs), but not in Hardware TMs (HTMs). Furthermore, STM implementations of this approach cannot be ported to HTMs easily. This paper investigates the feasibility of such reordering in HTMs, and presents two designs that are scalable, independent of the on-chip interconnect, require only minor modifications to each core, and add no execution overhead if no conflicts occur. The evaluation takes LogTM-SE as a base line and considers benchmarks with different levels of contention (transactional conflicts). The results show that the preferred design increases HTM performance by up to 17% when contention is low, 57% when contention is high, and never degrades performance. Finally, the designs are orthogonal to LogTM-SE; they require no modification to cache structures, and continue to support transaction virtualization, open and closed unbounded nesting, paging, thread suspension, and thread migration.

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An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

Zhou

Delaval

Robu

et al. 2018

Concurrency and Computation

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A parallel program needs to manage the trade-off between the time spent in synchronisation and computation. This trade-off is significantly affected by its parallelism degree. A high parallelism degree may decrease computing time while increasing synchronisation cost. Furthermore, thread placement on processor cores may impact program performance, as the data access time can vary from one core to another due to intricacies of the underlying memory architecture. Alas, there is no universal rule to decide thread parallelism and its mapping to cores from an offline view, especially for a program with online behaviour variation. Moreover, offline tuning is less precise. We present our work on dynamic control of thread parallelism and mapping. We address concurrency issues via Software Transactional Memory (STM). STM bypasses locks to tackle synchronisation through transactions. Autonomic computing offers designers a framework of methods and techniques to build autonomic systems with well-mastered behaviours. Its key idea is to implement feedback control loops to design safe, efficient, and predictable controllers, which enable monitoring and adjusting controlled systems dynamically while keeping overhead low. We implement feedback control loops to automate management of threads and diminish program execution time. KEYWORDSautonomic computing, feedback control, parallelism, synchronisation, thread mapping, transactional memory INTRODUCTIONMulti-core processors accelerate computation using high thread parallelism (number of simultaneously active threads). A program for multi-cores executes in parallel and needs to scale when the number of cores increases. However, writing a parallel application is difficult, as parallel programming encompasses all the difficulties of sequential programming and introduces extra problems on coordination of interactions among concurrently executing tasks. 1 High thread parallelism may shorten execution time, but it may potentially increase synchronisation time.Multi-core processors incorporate complex memory hierarchies, which consist of several levels of cache to alleviate penalties caused by the data access to main memory. Consequently, parallel applications need to evolve to efficiently exploit the potential of their underlying architecture.Depending on the level of cache where data are placed, access latency differs from different cores. To alleviate access latency, threads can be fixed to certain cores to improve their resource usage, eg, cache, main memory and interconnections.The conventional way to address synchronisation is via locks. However, locks are notorious for various issues such as deadlocks and the vulnerability to thread failures. 2,3 Furthermore, it is not straightforward to analyse interactions among concurrent operations. Transactional memory (TM) has emerged as an alternative parallel programming technique that handles synchronisation through transactions rather than locks. 4 Access to shared data is enclosed in transactions that are speculatively executed without b...

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Advanced Concurrency Control for Transactional Memory Using Transaction Commit Rate

Cited by 37 publications

References 7 publications

Adaptive Thread Scheduling Techniques for Improving Scalability of Software Transactional Memory

Adaptive Thread Scheduling Techniques for Improving Scalability of Software Transactional Memory

Improving Performance by Reducing Aborts in Hardware Transactional Memory

An autonomic‐computing approach on mapping threads to multi‐cores for software transactional memory

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