Adiabatic approach for charge restoration in low power digital circuits

Yadav, Ruchi; Bakshi, Amit; Chowdhury, Joy; Das, Jitendra Kumar

doi:10.1109/icisc.2018.8399117

Cited by 9 publications

(3 citation statements)

References 4 publications

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“…For comparative analysis, result is obtained through simulations at 10 MHz for the gates under study using conventional CMOS approach and the other two adiabatic techniques i.e. ECRL [30], [31] and PFAL [32], [33] as shown in Table 1. For other frequencies, the results are given in Table 2.…”

Section: Design Of Basic Gates Using Mpfalmentioning

confidence: 99%

Low power architecture of logic gates using adiabatic techniques

Sanadhya

Sharma

2022

IJEECS

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The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

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Section: Design Of Basic Gates Using Mpfalmentioning

confidence: 99%

Low power architecture of logic gates using adiabatic techniques

Sanadhya

Sharma

2022

IJEECS

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“…It implies that the energy produced in the capacitor is more than wasted during loading or discharging by the resistor. This shows that some energy deposited in the load is effectively transferred to the source of energy [3] [4] during discharge.…”

Section: B Adiabatic Switchingmentioning

confidence: 99%

“…P short = α(β/2) (V-2V th ) 3 *f *T rf (3) P leakage = (I diode + I subthreshold ) *V dd (4) α = Activity Factor, C = Load Capacitance, V dd =DC Voltage, f =Frequency of the clock, β= Gain Factor, T rf = Rise/Fall Time (gate inputs), V th = Threshold Voltage. Dynamic energy is the device's power consumption when constantly switching from one state to another.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

Anitha*¹

2019

IJRTE

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In today's electronic sector, low energy has appeared as a major feature. Power effectiveness is one of the most significant characteristics of contemporary, high-speed and mobile digital devices. Different methods are available to decrease energy dissipation at distinct stages of the planning method and have been applied. As the transistors count per device region continues to rise, while the switching energy does not rise at the same pace, power dissipation increases, and heat removal becomes more hard and costly. The power consumption of electronic appliances can be decreased by using various logic types. For such low-power electronic applications, adiabatic logic mode is very appealing. Using adiabatic logic, distinct powerefficient gates are intended in this document and contrasted for energy dissipation, propagation delay and no of the transistors used. In addition, the circuit developer can use these gates in the combinational and sequential circuits to develop low-power systems. The simulations of these gates are carried out in 90 nm technology using cadence virtuoso instrument.

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Low-Power Analysis of Full Adder and Subtractor Design Using Adiabatic Logic Styles

Akshitha¹,

Rajan²

2019

Lecture Notes in Electrical Engineering

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Adiabatic approach for charge restoration in low power digital circuits

Cited by 9 publications

References 4 publications

Low power architecture of logic gates using adiabatic techniques

Low power architecture of logic gates using adiabatic techniques

Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

Low-Power Analysis of Full Adder and Subtractor Design Using Adiabatic Logic Styles

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