Implementation of Energy Efficient gates using Adiabatic Logic for Low Power Applications

Abstract

In today's electronic sector, low energy has appeared as a major feature. Power effectiveness is one of the most significant characteristics of contemporary, high-speed and mobile digital devices. Different methods are available to decrease energy dissipation at distinct stages of the planning method and have been applied. As the transistors count per device region continues to rise, while the switching energy does not rise at the same pace, power dissipation increases, and heat removal becomes more hard and costly. The power consumption of electronic appliances can be decreased by using various logic types. For such low-power electronic applications, adiabatic logic mode is very appealing. Using adiabatic logic, distinct powerefficient gates are intended in this document and contrasted for energy dissipation, propagation delay and no of the transistors used. In addition, the circuit developer can use these gates in the combinational and sequential circuits to develop low-power systems. The simulations of these gates are carried out in 90 nm technology using cadence virtuoso instrument.

Low power architecture of logic gates using adiabatic techniques

“…Two phase adiabatic dynamic logic (2PADL) is used to design a carry lookahead adder which has the advantages of energy efficiency and lower switching power due to the usage of gate overdrive because of this feature it can be used in a variety of low-power very large scale integrated (VLSI) designs [7]. Further, energy efficient different gates are design using various adiabatic approach like CMOS, 2N2P, efficient charge recovery logic (ECRL) and PFAL adiabatic logic for low power applications [8]. A energy efficient AND/NAND and XOR/XNOR gates and carry lookahead adder are designed using noval charge sharing improved pass gate adiabatic logic (CSIPGL) technique which is operating uses four-phase power clock sources [9].…”