Addressing Test Generation Challenges for Configurable Processor Verification

Rimon, Michal; Lichtenstein, Yossi; Adir, Allon; Jaeger, I.; Vinov, Michael; Johnson, Scott; Jani, Dharmesh

doi:10.1109/hldvt.2006.319970

Cited by 4 publications

(1 citation statement)

References 6 publications

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“…The intelligence of this model-based [13] platform is reflected in its static checking of the analysis, sharing of unified analysis data from early modeling stages, and the auto-generation of code for the generator, checker, and reference model (RM), as well as its coverage. Sharing the unified analysis data allows the architecture performance in the functional verification and debugging stages to be explored.…”

Section: Introductionmentioning

confidence: 99%

A novel intelligent verification platform based on a structured analysis model

Xie¹,

Wang²,

Lian³

et al. 2013

Sci. China Inf. Sci.

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Section: Introductionmentioning

confidence: 99%