Best merge region growing normally produces segmentations with closed connected region objects. Recognizing that spectrally similar objects often appear in spatially separate locations, we present an approach for tightly integrating best merge region growing with nonadjacent region object aggregation, which we call hierarchical segmentation or HSeg. However, the original implementation of nonadjacent region object aggregation in HSeg required excessive computing time even for moderately sized images because of the required intercomparison of each region with all other regions. This problem was previously addressed by a recursive approximation of HSeg, called RHSeg. In this paper, we introduce a refined implementation of nonadjacent region object aggregation in HSeg that reduces the computational requirements of HSeg without resorting to the recursive approximation. In this refinement, HSeg's region intercomparisons among nonadjacent regions are limited to regions of a dynamically determined minimum size. We show that this refined version of HSeg can process moderately sized images in about the same amount of time as RHSeg incorporating the original HSeg. Nonetheless, RHSeg is still required for processing very large images due to its lower computer memory requirements and amenability to parallel processing. We then note a limitation of RHSeg with the original HSeg for high spatial resolution images and show how incorporating the refined HSeg into RHSeg overcomes this limitation. The quality of the image segmentations produced by the refined HSeg is then compared with other available best merge segmentation approaches. Finally, we comment on the unique nature of the hierarchical segmentations produced by HSeg.
Verification of a computer that implements a new architecture is especially difficult since no approved functional test cases are available. The logic design of the IBM RiSe System/6000 TII was verified mainly by a specially developed random test program generator (RTPG), which was used from the early stages of the design until Its successful completion. APL was chosen for the RiSe System/6000 RTPG implementation after considering the suitability of this programming language for modeling computer architectures, the very tight schedule, and the highly changeable environment in which RTPG would operate.T he ultimate goal of design verification is to ensure equivalence between a design and its functional specification. Strictly speaking, we can say that this goal can be achieved by exhaustive simulation or formal proof of correctness. The exhaustive simulation, in which all possible combinations of all inputs and memory elements of the design should be applied, can be done only for very small designs. Also, the state of the art of the formal techniques and the complexity of designs and specifications, usually written in English, do not allow utilization of the formal techniques in most industrial applications. 1 Despite significant progress
Image segmentation is a crucial part of image processing applications. Currently available approaches require significant computer power to handle large images. We present an efficient region growing algorithm for the segmentation of multi-spectral images in which the complexity of the most time-consuming operation in region growing, merging segment neighborhoods, is significantly reduced. In addition, considerable improvement is achieved by preprocessing, where adjacent pixels with close colors are gathered and used as initial segments. The preprocessing provides substantial memory savings and performance gain without a noticeable influence on segmentation results. In practice, there is an almost linear dependency between the runtime and image size. Experiments show that large satellite images can be processed using the new algorithm in a few minutes on a moderate desktop computer.
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