Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing

Abstract

The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face the communication scalability challenge while meeting tight power, area and latency constraints. Designers must address new challenges that were not present before. Defective components, the enhancement of application-level parallelism or power-aware techniques may break topology regularity, thus, efficient routing becomes a challenge.In this paper, uLBDR (Universal Logic-Based Distributed Routing) is proposed as an efficient logic-based mechanism that adapts to any irregular topology derived from 2D meshes, being an alternative to the use of routing tables (either at routers or at end-nodes). uLBDR requires a small set of configuration bits, thus being more practical than large routing tables implemented in memories. Several implementations of uLBDR are presented highlighting the trade-off between routing cost and coverage. The alternatives span from the previously proposed LBDR approach (with 30% of coverage) to the uLBDR mechanism achieving full coverage. This comes with a small performance cost, thus exhibiting the trade-off between fault tolerance and performance

A Reliable Routing Architecture and Algorithm for NoCs

“…Finally, faults may be limited to datapath components [34], or to links and crossbars [35] Unrestricted faults: A number of on-chip proposals tackle the problem of unconstrained faults. uLBDR [36] handles routing for any 2-D mesh topology without the need for routing tables. It adds logic to each input port, which facilitates routing around faulty links.…”

ReliNoC: A reliable network for priority-based on-chip communication

“…In this case, the packet cannot go to the East direction and should be detoured to another direction. To do so, we use Logic-Based Distributed Routing (LBDR) which is a fault tolerant routing algorithm proposed by Rodrigo et al in [7]. This routing is a logic-based mechanism which can be implemented on top of any distributed routing like XY to detour the faulty link.…”

“…Routing algorithms for fault-tolerant networks have been extensively explored for network level reconfiguration [5], [6], [7], [8]. These algorithms direct traffic around failed network components in a way that avoids network deadlock.…”

“…Although we must also accomplish this, we additionally reconfigures around faults using other methods as well. We adopt an implementation of the routing algorithm described in [7] for part of our network level fault recovery.…”

Cost Effective Routing Implementations for On-chip Networks

“…In order to offer a complete unicast solution, LBDR and the extensions, deroutes and forks, have been gathered in one single mechanism, called uLBDR (Universal Logic-Based Distributed Routing) [48]. LBDR is integrated as the core module of this mechanism, and the foundations have been extended to include the R xx routing bits, to reflect routing restrictions that prevent horizontal or vertical traversal of a router (EW , W E, N S and SN transitions).…”