Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

Matsutani, Hiroki; Koibuchi, Michihiro; Wang, Daihan; Amano, Hideharu

doi:10.1109/nocs.2008.4492722

Cited by 37 publications

(40 citation statements)

References 15 publications

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“…A number of power-gating schemes have been been proposed for NoC components, operating at different levels of granularity: routers [10], ports [11], VCs [12], buffers [8]. However, all such schemes suffer from accumulated wakeup times and excess energy spent in each power-gating event.…”

Section: Related Workmentioning

confidence: 99%

Power-Aware NoCs through Routing and Topology Reconfiguration

Parikh

Das

Bertacco

2014

Proceedings of the 51st Annual Design Automation Conference

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With the advent of multicore processors and system-on-chip designs, intra-chip communication demands have exacerbated, leading to a growing adoption of scalable networks-on-chip (NoCs) as the interconnect fabric. Today, conventional NoC designs may consume up to 30% of the entire chip's power budget, in large part due to leakage power. In this work, we address this issue by proposing Panthre: our solution deploys power-gating to provide long intervals of uninterrupted sleep to selected units. Packets that would normally use power-gated components are steered away via topology and routing reconfiguration, while Panthre provides low-latency alternate paths to their destinations. The routing reconfiguration operates in a distributed fashion and guarantees that deadlock-free routes are available at all times. At runtime, Panthre adapts to the application's communication patterns by updating its power-gating decisions. It employs a feedback-based distributed mechanism to control the amount of sleeping components and of packets detours, so that performance degradation is kept at a minimum. Our design is flexible, providing a mechanism that designers can use to tradeoff power savings with performance, based on application's requirements.Our experiments on multi-programmed communication-light workloads from the SPEC CPU2006 suite show that Panthre reduces total network power consumption by 14.5% on average, with only a 1.8% degradation in performance, when all processor nodes are active. At times when 15-25% of the processor cores are communication-idle, Panthre enables leakage power savings of 36.9% on average, while still providing connected and deadlock-free routes for all other nodes.

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Section: Related Workmentioning

confidence: 99%

Power-Aware NoCs through Routing and Topology Reconfiguration

Parikh

Das

Bertacco

2014

Proceedings of the 51st Annual Design Automation Conference

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“…To get out of such a dilemma, the researchers proposed many strategies from diverse points of view. The authors of [10,11] introduce power gating to shut down idle VCs. Although power gating can reduce the system static power consumption, it needs additional technology support.…”

mentioning

confidence: 99%

A Virtual Channel Allocation Algorithm for NoC

Bao

Xin

et al. 2017

ICST Transactions on Ambient Systems

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Virtual channel (VC) flow control proves to be an alternative way to promote network performance, but uniform VC allocation in the network may be at the cost of chip area and power consumption. We propose a novel VC number allocation algorithm customizing the VCs in network based on the characteristic of the target application. Given the characteristic of target application and total VC number budget, the block probability for each port of nodes in the network can be obtained with an analytical model. Then VCs are added to the port with the highest block probability one by one. The simulation results indicate that the proposed algorithm reduces buffer consumption by 14.58%~51.04% under diverse traffic patterns and VC depth, while keeping similar network performance.

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“…For instance, authors in [42] propose, instead of switching the whole router off, to decrease the available number of Virtual Channels (VCs) by switching some of them off when the traffic load is low. Other proposals stand by switching off huge parts of the router and enabling bypasses, which are simpler, thereby less power-hungry.…”

Section: Power-gatingmentioning

confidence: 99%

“…To solve this issue, some works, instead of switching all the buffers off in a given port, decrease the available resources (number of VCs) by switching some of the buffers off [42] or switch all buffers off and enable bypasses to preserve paths. In [43] authors propose to power routers off but enabling bypasses at powered off routers in order to enable a guaranteed path at each router.…”

Section: Related Workmentioning

confidence: 99%

Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

López¹,

José²

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Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks

Cited by 37 publications

References 15 publications

Power-Aware NoCs through Routing and Topology Reconfiguration

Power-Aware NoCs through Routing and Topology Reconfiguration

A Virtual Channel Allocation Algorithm for NoC

Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

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