ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

Lin, Haidang; Boecker, Charlie; Hossain, Masum; Tangirala, Shankar; Vu, Roxanne; Vamvakos, Socrates D.; Groen, Eric; Li, Simon; Choudhary, Prashant; Wang, Nanyan; Shibata, Masumi; Taghavi, Hossein; Ierssel, Marcus van; Maniyar, AdilHussain; Wodkowski, Adam; Brar, Kulwant; Nguyễn, Nam Thành; Desai, Shaishav

doi:10.1109/jssc.2021.3051109

Cited by 18 publications

(2 citation statements)

References 13 publications

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“…At 112 Gbps, only a 5-tap FFE is required to open the eye, well within the capabilities of an LR SERDES. Many long reach SERDES also implement CTLE and/or a decision feedback equalizer, which could further improve performance [38][39][40].…”

Section: Resultsmentioning

confidence: 99%

Monolithically integrated 112 Gbps PAM4 optical transmitter and receiver in a 45nm CMOS-silicon photonics process

Baehr-Jones,

Ardalan,

Chang

et al. 2023

Preprint

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We demonstrate a transmitter and receiver in a silicon photonics platform for O-band optical communication that monolithically incorporates a modulator driver, traveling-wave Mach-Zehnder modulator, control circuitry, photodetector, and TIA in the GlobalFoundries Fotonix™ (45SPCLO) platform. The transmitter and receiver show an open 112 Gbps PAM4 eye at a 4.3 pJ/bit energy efficiency, not including the laser. Extensive use of gain-peaking enables our modulator driver and TIA to achieve the high bandwidths needed in the 45 nm CMOS-silicon photonics process. Our results suggest an alternative to the frequent approach of bump-bonding BiCMOS drivers and TIAs to silicon photonics.

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Section: Resultsmentioning

confidence: 99%

Monolithically integrated 112 Gbps PAM4 optical transmitter and receiver in a 45nm CMOS-silicon photonics process

Baehr-Jones,

Ardalan,

Chang

et al. 2023

Preprint

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“…Ultra-high sample rate analog-to-digital converters (ADCs) operating at several tens of gigahertz are increasingly demanded in leading-edge instruments, optical communications, multiple-input multiple-output (MIMO) systems, and 6G communications [1][2][3][4][5][6]. Benefiting from the technology scale and digital architecture, successive approximation register (SAR) ADC shows prominent advantages in power efficiency and area occupation for high-speed and moderate-resolution designs.…”

Section: Introductionmentioning

confidence: 99%

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

Luan

Zheng

et al. 2022

Electronics

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This paper presents a real-time output 56 GS/s 8 bit time-interleaved analog-to-digital converter (ADC), where the full-speed converted data are output by 16-lane transmitters. A 64-way 8 bit asynchronous SAR array using monotonous and split switching strategy with 1 bit redundancy is utilized to achieve a high linearity and high-power efficiency. A low-power ring voltage-controlled oscillator-based injection-locked phase-locked loop combining with a phase interpolator-based time-skew adjuster is developed to generate the 8 equally spaced sampling phases. Digital gain correction, digital-detection-analog-correction offset calibration, and coarse–fine two-step time-skew calibration are combined to optimize the ADC’s performances. An edge detector and phase selector associated with a common near-end data-transmission position and far-end data-collection instant are designed to avoid reset competition and implement deterministic latency. Fabricated in a 28 nm CMOS process, the prototype ADC achieves an outstanding SNDR of 36.38 dB at 56 GS/s with a 19.9 GHz input, where 7.25 dB and 9.33 dB are optimized by offset-gain calibration and time-skew calibration, respectively. The ADC core occupies an area of 1.2 mm2 and consumes 432 mW power consumption.

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Advancing Baud Rate Receivers: On Multiple CTLE Parameters Background Adaptation

Tavares,

Lee

2024

IEEE Access

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ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET

Cited by 18 publications

References 13 publications

Monolithically integrated 112 Gbps PAM4 optical transmitter and receiver in a 45nm CMOS-silicon photonics process

Monolithically integrated 112 Gbps PAM4 optical transmitter and receiver in a 45nm CMOS-silicon photonics process

A 56 GS/s 8 Bit Time-Interleaved ADC in 28 nm CMOS

Advancing Baud Rate Receivers: On Multiple CTLE Parameters Background Adaptation

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