ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition

Safarpour, Mehdi; Inanlou, Reza; Charmi, Mostafa; Shoaei, O.; Silvén, Olli

doi:10.1109/tvlsi.2018.2821696

Cited by 2 publications

(2 citation statements)

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“…For example, the ultra-low power MCU ARM M0+ implementation by ST Microelectronics [3] draws 88 µA/MHz, while the ADC requires 40 µA at 10kS/s and 200 µA at 1MS/s. For wireless communications, long range backscatter technology has been demonstrated to dissipate only 70 µW at 868 MHz with 2.9 kbit/s [4], a low rate that may require exploiting sparse sampling as a low energy compression scheme, if feasible for the signal of interest [5]. With the aim being deep-sub-mW devices, multiple approaches have been proposed to improve 1 The low power ADC simulation model and software for the approach proposed in this paper are available from Github at https://github.com/NeuroFan/Algorithmic-SAR-ADC-simulation-files the energy efficiency of the ADC, ranging from device and process improvements to circuit level and architectural innovations [6,5,7].…”

Section: Introductionmentioning

confidence: 99%

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

2020

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This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles. The approach determines the required step size, and bypasses conversion cycles when signal activity is low, without compromising the precision or sampling rate. The required first-order predictions and boundary checkings are performed with simple digital circuits. A lowered number of cycles paired with reduced voltage variations across DAC capacitors yields power savings. The solution has been simulated in a 90 nm CMOS process using HSPICE, demonstrating a 10-bit tracking SAR ADC. The proposed ADC was examined with low activity signals such as EEG, ECG, etc. The results predict from 5.8 µW to 27.6 µW dissipation when the sampling rates range from 32 kHz to 800 kHz, respectively.

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Section: Introductionmentioning

confidence: 99%

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

2020

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“…Based on the CS theory, the number of measurements needed for exact signal reconstruction depends on the sparsity degree rather than bandwidth. Analog to Information Convertors (AIC) [2] are examples of devices that exploit signal sparsity for reduced sampling rates in the context of the CS framework [3]. A major issue with the compressive sensing framework is the computational complexity of CS reconstruction.…”

Section: Introductionmentioning

confidence: 99%

An Embedded Programmable Processor for Compressive Sensing Applications

Safarpour

Hautala

Silvén

2018

2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

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An application specific programmable processor is designed based on the analysis of a set of greedy recovery Compressive Sensing (CS) algorithms. The solution is flexible and customizable for a wide range of problem dimensions, as well as algorithms. The versatility of the approach is demonstrated by implementing Orthogonal Matching Pursuits, Approximate Messaging Passing and Normalized Iterative Hard Thresholding algorithms, all using a high-level language. Transported Triggered Architecture (TTA) framework is employed for the efficient implementation of macro operations shared by the algorithms. The performance of the CS algorithms on ARM Cortex-A15 and NIOS II processors has also been investigated, and empirical comparisons are presented. The flexible hardware design implemented on an FPGA achieves up to 7.80Ksample/s recovery at a power dissipation of 42μJ/sample and beats both ARM and NIOS in total power consumption.

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ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition

Abstract: IndexTerms-analog-digital conversion; analog-digital integrated circuits.

Cited by 2 publications

References 28 publications

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

An Embedded Programmable Processor for Compressive Sensing Applications

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