Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods

Abstract

This paper introduces a novel arithmetic tracking algorithm for successive approximation ADCs, and presents its analysis. The algorithm utilizes low activity signal periods to cut the ADC energy dissipation by reducing the number of required bit-cycles. The approach determines the required step size, and bypasses conversion cycles when signal activity is low, without compromising the precision or sampling rate. The required first-order predictions and boundary checkings are performed with simple digital circuits. A lowered number of cycles paired with reduced voltage variations across DAC capacitors yields power savings. The solution has been simulated in a 90 nm CMOS process using HSPICE, demonstrating a 10-bit tracking SAR ADC. The proposed ADC was examined with low activity signals such as EEG, ECG, etc. The results predict from 5.8 µW to 27.6 µW dissipation when the sampling rates range from 32 kHz to 800 kHz, respectively.

Run-time integrity monitoring of untrustworthy analog front-ends

“…The 8-bit arithmetic tracking successive approximation register ADC simulator from [8] was used for the A/D conversion of different types of input signals pertaining to three different applications 1 ; The ECG signal from the ECGSYN tool-set [9], readings of flow and level sensors from the secure water treatment system developed by iTrust in the centre for Research in Cyber Security at Singapore University of Technology and Design [10], and level and flow readings of airplane fuel tank sensors [11]. The obtained digital output in each of these cases was then analyzed and the slopes were calculated using Matlab.…”