Adaptive switching detection algorithm for iterative‐MIMO systems to enable power savings

Abstract

Key Points:• Adaptivity achieves optimal error rate performance with minimal power • Receiver adapts to conditions according to the mutual information thresholds • DVFS technique reduces the circuit power demands of the adaptive algorithm Input Multiple Output (MIMO) detection systems, which is to achieve optimal error rate performance with minimal power consumption. This is realized by proposing a new algorithm design that comprises multiple thresholds within the detector that, in real time, specify the receiver behavior according to the current channel in both slow and fast fading conditions, giving it adaptivity. This adaptivity enables energy savings within the system since the receiver chooses whether to accept or to reject the transmission, according to the success rate of detecting thresholds. The thresholds are calculated using the mutual information of the instantaneous channel conditions between the transmitting and receiving antennas of iterative-MIMO systems. In addition, the power saving technique, Dynamic Voltage and Frequency Scaling, helps to reduce the circuit power demands of the adaptive algorithm. This adaptivity has the potential to save up to 30% of the total energy when it is implemented on Xilinx®Virtex-5 simulation hardware. Results indicate the benefits of having this "intelligence" in the adaptive algorithm due to the promising performance-complexity tradeoff parameters in both software and hardware codesign simulation.

Power Performance Analysis of the Iterative-MIMO Adaptive Switching Algorithm Detector on the FPGA Hardware

“…Since this paper studies the energy efficiency of the system instead of maximizing the throughput, it is assumed that the system adopts low channel utilization policy, where packets are decoded at a maximum time of 20 µs. The energy trends are shown in Figure 4, where the dynamic and static energy consumption are compared on Xilinx®Virtex-5 [7] and Virtex-7. By comparing Figure 4(a), similar trends for scaling up the voltage in both chips can be observed, whereby, the energy is directly proportional to the voltage.…”

“…The Adaptive Switching Algorithm [7] is demonstrated with two well-known detection algorithms, namely the Fixed Sphere Decoder (FSD) [6], and the Vertical-Bell Laboratories Layered Space-Time [1] with the Zero Forcing (V-BLAST/ZF) technique. Switching between algorithms is determined by thresholds pre-calculated from the MI between the transmitter and the receiver, according to the real-time channel conditions.…”

“…This paper builds on the work of [7] by implementing the Adaptive Switching Algorithm onto an Field Programmable Gate Arrays (FPGA) hardware, in hope to gain further power and energy savings during hardware implementation. This gain is on top of the energy savings due to the switching receiver described in [7]. The FPGA is chosen as an exemplar platform for rapid prototyping purposes.…”

FPGA design of box‐constrained DCD‐based detector for large‐scale MIMO systems

“…To meet these demands, it is expected that future communication systems, i.e., beyond 4G or 5G systems, will reach a faster data rate at gigabit‐scale over the next few years. The conventional small‐size multiple‐input multiple‐output (MIMO) detectors have been proposed in the literature [ Rao et al , ; Tadza et al , ; Salari et al , ; Cong et al , ]. All these architectures require matrix inversion.…”

CELLA: FPGA Based Candidate Execution with Low Latency Approach for Soft MIMO Detector

“…It provides low decoding latency and it is suitable for fully pipelined hardware implementation. In order to achieve optimal error rate performance with minimal power consumption, an adaptive switching detection algorithm is designed to incorporate multiple thresholds within the detector, which is implemented in XilinxVirtex-5 simulation hardware [6].…”