Programmable frequency dividers with wide modulus range and 50% output duty cycle are highly desirable in the design of frequency synthesizers and phase-locked loops. However, most of the conventional dividers cannot simultaneously achieve a 50% output duty cycle and full modulus range. A programmable frequency divider with a full modulus range, 50% output duty cycle and low phase noise is presented in this paper. To achieve a 50% output duty cycle, the divider employs a novel programmable down-counter based on a modified D flip-flop with a load function. The divider, which was fabricated in a standard 0.18-μm CMOS process, achieves a full 1 to 256 modulus range, 50% output duty cycle, and can operate up to 2.3 GHz with a 1.8-V supply voltage and a power consumption of 3.4 mW. The measured phase noise is-141 dBc/Hz at the frequency offset of 1 MHz when the divider is working at a 1-GHz operational frequency and a division ratio of 10.
A field-programmable gate array (FPGA) implementation of a new algorithm for multiuser detection (MUD) is presented in this paper. This FPGA design is based on the Dichotomous Coordinate Descent (DCD)algorithm. The DCD algorithm allows the multiplication-free solution of the normal equations appearing in the MUD problem. This results in an area-efficient FPGA design that requires about 400 slices and offers a constant throughput over a signal-to-noise ratio range. Results obtained from the fixed-point FPGA implementation are compared with those of a floating-point implementation. The biterror-rate performance comparison shows good match of the results for as large number of users as 50.
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