Adaptive Power Optimization of On-chip SNUCA Cache on Tiled Chip Multicore Architecture Using Remap Policy

ACCURATE: Accuracy Maximization for Real-Time Multicore Systems With Energy-Efficient Way-Sharing Caches

“…Authors in [25], [26] surveyed a number of performance cognizant low power on-chip cache design techniques along with their pros and cons. By employing Gated-VDD [27] at the circuit level to power gate the cache lines, a prediction based energy-efficient cache was proposed in [28] for TCMP static non-uniform cache access (SNUCA) based architecture, that incurs a remapping technique for the gated cache lines. To reduce cache leakage power significantly, a bank shutdown policy based on run-time bank usages was proposed in [29].…”

“…V-B). Most of the prior analyses of the PARSEC regarding cache access patterns have shown the sufficiency of using 70 − 100M clock cycles, as by considering this analysis overall trend of cache access patterns can be realized for most of the PARSEC applications [5], [32], [33], [28].…”

“…Algorithm 1 takes the following parameters as the inputs: Interval length, Sleep T hr, T urn ON OH, and #available higher versions of O i . During execution, Algorithm 1 checks the LLC usages periodically at the end of each Interval length number of cycles, which is set by considering prior analyses of LLC usages [33], [32], [28]. Sleep T hr is a minimum threshold value for a slack-span which is also known as the processor's break-even time [39], and whose value is architecture dependent.…”

“…The incurred energy overheads for implementing the online mechanism of ACCURATE are also derived from McPAT. By considering prior empirical analysis based on cache locality [28], [33], the length of an interval (Interval length in Algorithm 1) is set to 2 million clock cycles. To set P OW ER U P and P OW ER DOW N in Algorithm 5, the range of the ratio for nine PARSEC applications was observed over 80 million clock cycles (within RoI), while applying FS-DAM at the LLC.…”