2014 International Conference on Electronics and Communication Systems (ICECS) 2014
DOI: 10.1109/ecs.2014.6892719
|View full text |Cite
|
Sign up to set email alerts
|

Cache capacity and its effects on power consumption for tiled chip multi-processors

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1
1
1

Citation Types

0
5
0

Year Published

2018
2018
2024
2024

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(5 citation statements)
references
References 13 publications
0
5
0
Order By: Relevance
“…Address removal. Algorithm 1 presents a typical iterative framework for finding a minimal eviction set with O(|E| 2 ) complexity [33], where |E| denotes the cardinality of the initial set E. In each iteration, the attacker determines whether a candidate address e in the initial set E can be removed (lines [1][2][3][4][5][6][7][8][9][10][11]. Removing e should not make the remaining E insufficient for evicting x from the cache.…”
Section: B Minimal Eviction Setmentioning
confidence: 99%
See 1 more Smart Citation
“…Address removal. Algorithm 1 presents a typical iterative framework for finding a minimal eviction set with O(|E| 2 ) complexity [33], where |E| denotes the cardinality of the initial set E. In each iteration, the attacker determines whether a candidate address e in the initial set E can be removed (lines [1][2][3][4][5][6][7][8][9][10][11]. Removing e should not make the remaining E insufficient for evicting x from the cache.…”
Section: B Minimal Eviction Setmentioning
confidence: 99%
“…The energy consumption of a cache is mainly composed of two parts: static power and dynamic power. Static power is generally referred as leakage power of the cache and dynamic power is consumed when the cache is accessed [7]. PhantomCache only affects the dynamic power of LLC because it only increases the cache activity during cache access.…”
Section: J Energy Overheadmentioning
confidence: 99%
“…A computation interacts with memory in different ways as it moves through the levels of a memory hierarchy. Cache misses significantly influence power and energy consumption [31]. The cache, typically in SRAM technology, is known to be much more power efficient than DRAM-based main memory.…”
Section: Cache Miss Analysis and Other Memory Trendsmentioning
confidence: 99%
“…They have surveyed various cache tuning techniques based on two categories, offline static cache tuning and online dynamic cache tuning, ranging from hardware support to cache tuning techniques. In [46] the effect of power and performance are analyzed by reducing cache capacity. Reducing cache size in some applications give significant energy saving in order of 3.17% and 24.16% in dynamic and static energy respectively while degrade the performance by increasing cache misses.…”
Section: Microarchitectural Power Savingmentioning
confidence: 99%