2013
DOI: 10.1016/j.neunet.2013.02.009
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Adaptive Neuromorphic Architecture (ANA)

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Cited by 40 publications
(6 citation statements)
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“…The circuit’s resonance frequency, determined by the staircased L ( q ) ( Figure 3 ) , increases itself with the increased number of oncoming stimulus pulses. This simulation in Figure 8 a agrees with our experiment in Figure 8 b on a hardware emulator built with a dsPIC30F2011 microcontroller, an MCP4261 digital potentiometer and a differential 12-bit ADC converter [ 15 ].…”
Section: Simulations and Experiments Of A Coil Core Meminductor For N...supporting
confidence: 85%
See 1 more Smart Citation
“…The circuit’s resonance frequency, determined by the staircased L ( q ) ( Figure 3 ) , increases itself with the increased number of oncoming stimulus pulses. This simulation in Figure 8 a agrees with our experiment in Figure 8 b on a hardware emulator built with a dsPIC30F2011 microcontroller, an MCP4261 digital potentiometer and a differential 12-bit ADC converter [ 15 ].…”
Section: Simulations and Experiments Of A Coil Core Meminductor For N...supporting
confidence: 85%
“…Taking amoebae as an example, they display memorizing, timing and anticipating mechanisms, which may represent the origins of primitive learning. A circuit element with memory can be used to mimic these behaviors in terms of being plastic according to the dynamic history [ 13 , 14 , 15 ].…”
Section: Simulations and Experiments Of A Coil Core Meminductor For N...mentioning
confidence: 99%
“…For convenience, we use conductance, which is proportional to synaptic weight as used in computer science or synaptic strength as used in neuroscience, when we refer to memristor device. two-terminal devices using various material systems [13]- [19], [38]- [42]. Fig.…”
Section: A Memristor As Synapsementioning
confidence: 99%
“…However, this may not be practical in real life situations. Recent progresses in designing adaptive neuromorphic architectures suggest (Wang et al, 2013) that in the next future will be possible to overcome this problem by implementing adaptive temporal binning schemes in hardware. By using such adaptive architectures, it may be possible to design acquisition hardware that self-adjusts its inherent parameters (for instance, the working frequency of the sample-and-hold circuit) naturally following the neural activity variability.…”
Section: Discussionmentioning
confidence: 99%