Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition

Abstract

Abstract-A neuromorphic chip that combines CMOS analog spiking neurons and memristive synapses offers a promising solution to brain-inspired computing, as it can provide massive neural network parallelism and density. Previous hybrid analog CMOS-memristor approaches required extensive CMOS circuitry for training, and thus eliminated most of the density advantages gained by the adoption of memristor synapses. Further, they used different waveforms for pre and post-synaptic spikes that added undesirable circuit overhead. Here we describe a hardware architecture that can feature a large number of memristor synapses to learn real-world patterns. We present a versatile CMOS neuron that combines integrate-and-fire behavior, drives passive memristors and implements competitive learning in a compact circuit module, and enables in-situ plasticity in the memristor synapses. We demonstrate handwritten-digits recognition using the proposed architecture using transistor-level circuit simulations. As the described neuromorphic architecture is homogeneous, it realizes a fundamental building block for large-scale energy-efficient brain-inspired silicon chips that could lead to next-generation cognitive computing.

Dendritic-Inspired Processing Enables Bio-Plausible STDP in Compound Binary Synapses

“…Consequently, it is natural to envision a verylarge-scale integrated (VLSI) Neuromorphic SoC built using CMOS neurons and RRAM synapses. Few research groups, including ours, have developed prototype chips and demonstrated such neural motifs with small-scale spiking neural networks [10], [11], [45]. In these works, analog-like conductance modulation capability that supports continuous weight change is required for effective STDP learning [2], [10].…”

“…Further, these devices have shown low-energy consumption to change their states and very compact layout footprint [4]- [9]. Hybrid CMOS-RRAM analog very-largescale integrated (VLSI) circuits have been proposed [10], [11] [20,21] to achieve dense integration of CMOS neurons and emerging devices for neuromorphic system-on-a-chip (NeuSoC). Fig.1a illustrates a NeuSoC architecture where a three layer fully-connected spiking neural network is envisioned.…”

Energy-Efficient CMOS Memristive Synapses for Mixed-Signal Neuromorphic System-on-a-Chip

“…The memristive synapse, for the given sizing for M 1 , realizes LRS and HRS resistances of 0.4M Ω and 16M Ω respectively, providing significant improvement over contemporary memristive devices. As detailed in [22], [30], the traditional subthreshold neuron designs are not suitable for driving memristive load. The opamp-based integrate-andfire neurons with winner-take-all STDP learning interface from author's prior work in [30] can directly be adapted to interface with the presented synapses; higher LRS resistance will further help simply opamp design.…”

Hardware design of LIF with Latency neuron model with memristive STDP synapses

“…11A. This three neurons and two synapses system is widely used for describing and analyzing the behaviour of neural circuits [39], [64], [65]. Moreover, the low complexity of the system allows to perform an electrical simulation.…”

“…many studies have been made to exploit memristors with the purpose of realizing plastic synapses within neuromorphic systems [29,32,33,34,35,36,37,38,39].…”