Adaptive demand‐aware work‐stealing in multi‐programmed multi‐core architectures

Abstract

SUMMARYModern multi-core computers often execute multiple programs concurrently, but traditional work-stealing schedulers assume that only a single program executes at a time. If multiple work-stealing programs run on a multi-core computer concurrently, the performance of these co-located programs is poor and unbalanced due to the interference among their workers. To relieve this problem, this paper proposes demand-aware work-stealing (DWS) for a single work-stealing program. If multiple programs that adopt DWS run simultaneously on a multi-core system, the computation resources are evenly allocated to the co-located programs at the beginning. At runtime, if a program does not need all its allocated cores, it donates its free cores. Otherwise, if a program needs more cores, it steals the free cores donated by its co-located programs. In addition, each program that adopts DWS dynamically puts its workers to sleep and wakes them up according to the number of its queued tasks. Experimental results show that DWS can improve the co-located programs' performance up to 42.6% and can also balance the performance of the co-located programs compared with traditional work-stealing.

Toward multi-programmed workloads with different memory footprints: a self-adaptive last level cache scheduling scheme

“…For multi-programmed workloads, there are numerous papers studied the performance optimization. The prior work covers relieving memory contention [10,11], workload balance [12,13], power related optimization [14]. In [11], a memory scheduling algorithm called time-based least memory intensive scheduling was proposed according to the memory contention situation.…”

“…[10] proposed the adaptive time-based least memory intensive scheduling. Chen et al [12] proposed a demand-aware work-stealing task scheduler, with which a work-stealing program uses cores according to its realtime demand, then they presented the adaptive version in [13]. In [31], a fast, automated technique was proposed for accurate on-line estimation of the performance and power consumption of interacting processes in a multi-programmed, multi-core environment.…”

“…Most of recent researches on hybrid SRAM and DRAM caches focus mainly on enhancing the overall performance of SRAM (resp., DRAM) by utilizing the merit of DRAM (resp., SRAM). There are also many papers devoted to investigating workload performance: (1) For multi-programmed workloads, prior work discussed the issues of relieving memory contention [10,11], workload balance [12,13] and power related optimization [14]; (2) To improve the performance of memory-intensive workloads, many solutions (e.g., architecture design [15][16][17], OS level method [18][19][20] and feedback control [21,22]) have also been proposed; (3) In the cache system, the improved cache architectures [4,9,23,24] and 3D-stacked DRAM technologies [25][26][27] are used to achieve better workload performance; and so on (a broader overview of related work will be covered in Section 2). Instead, little attention has been paid to designing a last level cache (LLC) scheduling scheme for multi-programmed workloads with different memory footprints.…”