Adapting Interconnect Technology to Multigate Transistors for Optimum Performance

Impact of interconnect variability on circuit performance in advanced technology nodes

“…The predictive libraries for the 11 nm technology node are built based on NANGATE 45 nm libraries [9], and scaling factors deduced from ITRS similar to prior work [1,2]. The predictive technology models (PTM) for the 11 nm FinFET transistors are taken from [10].…”

“…The interconnect files for copper wires with TaN barrier-liner are designed using minimum width and spacing presented in Table I. All other BEOL design parameters are taken from [2].…”

“…Based on the netlist, a static parasitic extraction file (.spef) is generated which defines the RC components of every interconnect segment in the physical design under study. The placement and route information of these two circuit blocks under study are discussed in detail in [2]. This netlist is then converted to an HSPICE file [13], which consists of a critical path SPICE equivalent, to enable a quick analysis as opposed to converting the whole design to HSPICE.…”

“…The effective wire capacitance for every net including variability is modeled using empirical formulae from [19]. Detailed implementation of the wire resistance and capacitance models are defined in [2].…”

“…The reason behind this being, faster device switching speeds in the front-end-of-line (FEOL) technology, complemented with a back-end-of-line (BEOL) technology which does not scale in terms of parasitic resistancecapacitance (RC) delay in advanced technology nodes. Circuit performance studies in literature have shown that interconnect parasitics are getting worse with scaling and negatively impacting performance [1,2]. In the sub-20 nm technology node, the sensitivity of circuit performance to interconnect parasitics has increased, ergo, the sensitivity to interconnect variability has also increased.…”