Impact of interconnect variability on circuit performance in advanced technology nodes

Prasad, Divya; Pan, Chenyun; Naeemi, Azad

doi:10.1109/isqed.2016.7479234

Cited by 11 publications

(4 citation statements)

References 14 publications

(25 reference statements)

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“…IR drop come from the electrical potential difference between the two ends of an operating phase during current flow, signal delay mean the time required for a signal to propagate from one side to the other. These are major causes of performance degradation [28][29][30][31][32]. The scaling down of Si MOS-FET process has been accelerating, these days ultrafine 3 nm processes are being developed.…”

Section: Post-layout Simulationmentioning

confidence: 99%

Electronic design automation requirements for R2R printing foundry

Kim¹,

Kim²

2022

Flex. Print. Electron.

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Roll-to-roll (R2R) printed electronic devices have been in the spotlight as a technology that can replace Si-based semiconductors for decades, and research is being actively conducted globally. The printed electronic devices can be applied to a variety of applications, so the demand for printed electronic devices is expected to reach over USD 20.7 billion in 2025 at a compound annual growth rate (CAGR) of 21.5 percent. As the new ink materials and printing technologies that are being researched are commercialized, foundry companies of the printed electronics should provide the flow to design circuits using commercial electronic design automation (EDA) tools. This review paper describes the key parameters of the process design kit (PDK), design rules and the device SPICE model. We cover the factors that need to be considered when a fabless company develops circuits using the R2R process, the design methodology from the beginning of the design to the final graphic data stream (GDS) completion stage, and other essential technologies that must be overcome in this process. We describe the full custom design flow for analog integrated circuits (ICs) and automatic placement and routing based design of digital integrated circuits.

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Section: Post-layout Simulationmentioning

confidence: 99%

Electronic design automation requirements for R2R printing foundry

Kim¹,

Kim²

2022

Flex. Print. Electron.

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“…This is due to the increased delay sensitivity to the interconnect parasitic [4]. Figure 1 illustrates the escalating interconnect Resistance-Capacitance (RC) delay with nodes scaling.…”

Section: Delay Sensitivity In Advanced Technology Nodesmentioning

confidence: 99%

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

et al. 2017

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Abstract:As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical designers and electronic design automation (EDA) providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR). An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP) technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics' physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS) and total negative slack (TNS) improved up to 13% and 56%, respectively, compared to the baseline flow.

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“…Different advanced packaging technologies, such as chip stacking, wafer stacking, and through-silicon vias (TSVs), enable the heterogeneous integration of chips with different technology nodes in the same package. For heterogeneous integration, 3D ICs are considered one of the most promising technologies for the future, while traditional packaging technology is facing challenges such as long wiring, high power consumption, and large form factor [4,5]. In addition, 3D ICs can provide higher integration density, lower power consumption, and low RC delay [6,7].…”

Section: Introductionmentioning

confidence: 99%

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application

Huang,

Lin,

Hsiung

et al. 2023

Nanomaterials

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Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper–copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

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Impact of interconnect variability on circuit performance in advanced technology nodes

Cited by 11 publications

References 14 publications

Electronic design automation requirements for R2R printing foundry

Electronic design automation requirements for R2R printing foundry

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application

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