Achieving Routing Integrity in Analog Layout Migration via Cartesian Detection Lines

Chi, Hao-Yu; Lin, Zi-Jun; Hung, Chia-Hao; Liu, Chien-Nan Jimmy; Chen, Hung-Ming

doi:10.1109/iccad45719.2019.8942088

Cited by 2 publications

(3 citation statements)

References 22 publications

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“…In the second set of the experiments, we intended to migrate the folded-cascode opamp) and variable-gain amplifier (VGA) from the UMC 90nm technology to the UMC 65nm technology. After performing block-level P&R migration with topology preservation based on the methodology presented in [3], we conducted the experiment on block-level P&R refinement with and without bend minimization. Table 4 gives the experimental comparison for both analog circuits.…”

Section: Experimental Results For Block-level Pandr With Preservation Amentioning

confidence: 99%

“…We apply the analog layout migration method using the model of Cartesian detection lines (CDL) [3] to block-level P&R with topology preservation and refinement. The modified flow is shown in Figure 10.…”

Section: Block-level Pandr With Topology Preservation and Refinementmentioning

confidence: 99%

“…After performing block-level P&R migration with topology preservation based on the methodology presented in [3], we further propose to refine the migrated P&R by minimizing routing bends. Excessive routing bends may introduce more vias, which leads to serious parasitic effects and degrades circuit performance.…”

Section: Block-level Pandr Refinement With Bend Minimizationmentioning

confidence: 99%

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