Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

Abstract

We achieved 635/250µA/µm@Ioff=20pA/µm unstrained FuSI/HfSiON nMOS/pMOS devices (Vdd=1.1V, Ioff=20pA/µm, Jg=20/8 mA/cm 2 ) representing a 20%/2% device improvement enabling 10% power delay improvement compared to our previous report [1]. This was reached by a careful optimization of the nitrogen content into our HfSiON gate dielectric (to be 3-6%). Second, we demonstrate that the nitrogen content impacts not only the device performance but also the gate leakage current, the gate oxide integrity as well as PBTI and NBTI. We also report for the first time a 0.8 nm EOT HfSiON dielectric with Ni-FuSI gate and its impact on ring oscillator delay resulting in 9ps delays. This is an absolute record for any CMOS with metal gate to date.

EOT sub-nanométrico y degradación de la movilidad: ¿hacia un límite físico con las técnicas de fabricación modernas?

“…• C con O 2 [12]. Una capa de Poly-Si (100 nm) es depositada sobre la capa de HfSiON con "Chemical Vapor Deposition (CVD)" a 700…”

“…La concentración de N permite aumentar el valor del κ del HfSiON [12] así que podemos alcanzar un EOT muy fino también con este tipo de procesamiento (alta temepratura o "high thermal budget"). Tenemos que tomar también en cuenta el efecto del N en la capa de SiO 2 .…”

Investigation of PDA process to improve electrical characteristics of HfO<inf>x</inf>N<inf>y</inf> High-k dielectric formed by ECR plasma oxidation of HfN

“…HfO x N y is the most promising so far as the next generation high-k gate insulator materials [1][2][3][4][5][6][7][8][9][10][11][12][13]. In order to suppress the interfacial layer (IL) formation with relatively low dielectric constant and to make the equivalent oxide thickness (EOT) thinner, electron cyclotron resonance (ECR) plasma oxidation of HfN thin film has been proposed [14,15].…”