Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques

Tannir, Dani; Ya, Wang

doi:10.1145/2890500

Cited by 14 publications

(10 citation statements)

References 12 publications

(7 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…We follow a similar comparison methodology as in prior inductor and modeling optimization works [51][52][53][54][55], where the commercial EM tool is used as the reference to validate the accuracy of the proposed model, and SPICE is used to present the performance of the optimized design. In the following simulation results, we will present the effectiveness of the proposed machine learning model, design and optimization, and the application in DC-DC converter design.…”

Section: Simulation Resultsmentioning

confidence: 99%

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Wen

Xiao

Chen

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

The conventional on-chip spiral inductor consumes a significant top-metal routing area, thereby preventing its popularity in many on-chip applications. Recently through-silicon-via (TSV) based inductor (also known as TSV-inductor) with a magnetic core has been proved to be a viable option for the on-chip DC-DC converter. The operating conditions of these inductors play a major role in maximizing the performance and efficiency of the DC-DC converter. However, there is a critical need to study the design and optimization details of magnetic core TSV-inductors with the unique 3D structure embedding magnetic core. This paper aims to provide a clear understanding of the modeling details of a magnetic core TSV-inductor and a design and optimization methodology to assist efficient inductor design. Moreover, a machine learning assisted model combining physical details and artificial neural network (ANN) is also proposed to extract the equivalent circuit to further facilitate DC-DC converter design. Experimental results show that the optimized TSV-inductor with the magnetic core and air-gap can achieve inductance density improvement of up to 7.7 × and quality factor improvements of up to 1.6 × for the same footprint compared with the TSV-inductor without a magnetic core. For on-chip DC-DC converter applications, the converter efficiency can be improved by up to 15.9% and 6.8% compared with the conventional spiral and TSV-inductor without magnetic core, respectively.

show abstract

Section: Simulation Resultsmentioning

confidence: 99%

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Wen

Xiao

Chen

et al. 2022

ACM Trans. Des. Autom. Electron. Syst.

View full text Add to dashboard Cite

show abstract

“…e power transistor works as short circuit or as an open circuit depending on whenever the signal command u(t) equals 1 or0. Along switching time, boost inverter equivalent circuit shown by Figure 1 takes two forms as shown by Figures 2(a) and Figure 2(b) [14]. During the ON state, the transistor behaves like a short and no current flows through the diode.…”

Section: Fundamentals Of a Dc-dc Boost Invertermentioning

confidence: 99%

“…is increases considerably the computing time, and a great amount of patience is required to establish adequate results. Because of the high switching frequency of the PWM technique [14], to solve the model of a DC-DC boost inverter, an integration step smaller than one microsecond is required. is makes the integration process time consuming even for short simulations.…”

Section: Introductionmentioning

confidence: 99%

Fast Simulation and Chaos Investigation of a DC‐DC Boost Inverter

Dhifaou

Brahmi

2021

Complexity

View full text Add to dashboard Cite

Intensive and repetitive simulations are required to study static and dynamic behaviours of systems. Particular phenomena such as bifurcation and chaos require long simulation times and analysis. To check the existence of bifurcations and chaos in a dynamic system, a fine-tuning procedure of a bifurcation parameter is to be carried out. This increases considerably the computing time, and a great amount of patience is needed to obtain adequate results. Because of the high switching frequency of a boost inverter, the integration process of the dynamic model used to describe it uses an integration step that is in general less than one microsecond. This makes the integration process time consuming even for a short simulation. Thus, a fast, but accurate, method is suitable to analyse the dynamic behaviour of the converter. This work contains two topics. First, we develop a like-discrete integration process that permits precise results in a very fast manner. For one switching period, we compute only two or a maximum of three breaking points depending on whether we treat a continuous conduction mode (CCM) or a discontinuous conduction mode (DCM) of the inductor current. Furthermore, with each segment of the dynamic trajectory, an exact analytic formula is associated. The second goal is to use this result to develop a discrete iterative map formulated as in standard discrete time series models. The Jacobian matrix of the found iterative map is defined and used to compute Lyapunov exponents to prove existence of chaos. Performance of the developed study is positively evaluated by using classical simulations and fine-tuning a bifurcation parameter to detect chaos. This parameter is the desired reference of the inductor current peak. Results show that the proposed scheme is very fast and accurate. The study can be easily extended to other switching topologies of DC-DC inverters.

show abstract

“…BSIM4 models were also used for other prior research studies on power supply circuits. 31,32) In BSIM4 models, all capacitances are derived from the charges to ensure charge conservation; hence, the effect of a feedback component is taken into consideration.…”

Section: Proposed Layout Of Multipillar-type Vertical Bc Mosfetmentioning

confidence: 99%

Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET

Itoh

Endoh

2018

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

In this paper, we present a novel transistor layout of multi pillar-type vertical body-channel (BC) MOSFET for cascode power switches for improving the efficiency and compactness of CMOS DC-DC converters. The proposed layout features a stacked and multifingered layout to suppress the loss due to parasitic components such as diffusion resistance and contact resistance. In addition, the loss of each MOSFET, which configures cascode power switches, is analyzed, and it is revealed that the total optimum gate width and loss with the high-side (HS) n-type MOSFET topology are 27 and 16% smaller than those with the HS p-type MOSFET topology, respectively. Moreover, a circuit simulation of 2.0 to 0.8 V, 100 MHz CMOS DC-DC converters with the proposed layout is carried out by using experimentally extracted models of BSIM4 60 nm vertical BC MOSFETs. The peak efficiency of the HS n-type MOSFET converter with the proposed layout is 90.1%, which is 6.0% higher than that with the conventional layout.

show abstract

Accurate Modeling of Nonideal Low-Power PWM DC-DC Converters Operating in CCM and DCM using Enhanced Circuit-Averaging Techniques

Cited by 14 publications

References 12 publications

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Magnetic Core TSV-Inductor Design and Optimization for On-chip DC-DC Converter

Fast Simulation and Chaos Investigation of a DC‐DC Boost Inverter

Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET

Contact Info

Product

Resources

About