Accurate area and delay estimators for FPGAs

Abstract

We present an area and delay estimator in the context of a compiler that takes in high level signal and image processing applications described in MATLAB and performs automatic design space exploration to synthesize hardware for a Field Programmable Gate Array (FPGA) which meets the user area and frequency specifications. We present an area estimator which is used to estimate the maximum number of Configurable Logic Blocks (CLBs) consumed by the hardware synthesized for the Xilinx XC4010 from the input MATLAB algorithm. We also present a delay estimator which finds out the delay in the logic elements in the critical path and the delay in the interconnects. The total number of CLBs predicted by us is within 16% of the actual CLB consumption and the synthesized frequency estimated by us is within an error of 13% of the actual frequency after synthesis through Synplify logic synthesis tools and after placement and routing through the XACT tools from Xilinx. Since the estimators proposed by us are fast and accurate enough, they can be used in a high level synthesis framework like ours to perform rapid design space exploration.

A Verifiable High Level Data Path Synthesis Framework

“…Table III Node size refers to the number of operations in the CDFG. All the benchmarks were verified with three different input variable wordlengths (8,16 and 32 bits). The benchmarks have maximum of twenty eight operations (nodes).…”

“…In [7], area, time, power models are given for Xilinx IP core which is integrated to FANTOM design automation tool. In [8], an estimation technique is proposed dealing with a MATLAB specification.…”

Macro-models for high-level area and power estimation on FPGAs

“…However, routing and flip-flop costs are not taken into account. Although [6] considers both datapath and control logic, it uses a table to store the operator area for different bits instead of a general function. All of them estimate the logic synthesis area instead of the post layout area after place and route and thus result in larger deviation for the real circuit.…”

An area estimation methodology for FPGA based designs at systemc-level

“…These activities can be roughly partitioned in two sets: those extracting information from RTL descriptions (VHDL, Verilog) and those extracting information form behavioral level descriptions. In the latter case, the problem is faced by translating behavioral descriptions (Matlab [5,6], other [7,8]) into VHDL-RT [5,6] or DFG [7]. Though these transformations are required whenever closefitting results are needed, the effort necessary to transform a high-level model into a more detailed model is not currently justified.…”