Accurate and efficient extraction of interconnect circuits for full-chip timing analysis

Basel, M.

doi:10.1109/wescon.1995.485263

Cited by 8 publications

(2 citation statements)

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“…Note that 12x corresponds to 30 of the area on layer i , 1 being occupied. 3 We observe that, in addition to the strong shielding e ect on Ci;i,2 due to the ground or samelayer neighbors, more crossunders on layer i , 1 imply less signi cant Ci;i,2. When there are twelve crossunders and a bottom ground, Ci;i,2=Ci;i = 0 : 4 with no neighbors on layer i, and 0:2 with two neighbors on layer i.…”

Section: Coupling Between Wires On Layer I and Wires On Layer I mentioning

confidence: 70%

Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

Cong

Het²,

Kahng

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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This paper addresses post-routing capacitance extraction during performance-driven layout. We rst show h o w basic drivers in process technology planarization and minimum metal density requirements actually simplify the extraction problem; we do this by proposing and validating ve foundations" through detailed experiments with representative 0 : 18m process parameters and a 3-D eld solver. We then present a simple yet accurate 2 1 2-D extraction methodology directly based on the foundations. This methodology has been productized and is being shipped with the Cadence Silicon Ensemble 5.0 product. We conclude that the 2 1 2-D approach has su cient accuracy for current and near-term process generations.

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Section: Coupling Between Wires On Layer I and Wires On Layer I mentioning

confidence: 70%

Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

Cong

Het²,

Kahng

et al. 1997

Proceedings of the 34th Annual Conference on Design Automation Conference - DAC '97

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“…But in parasitic parameter extraction, almost all of the tools invoke the flat extraction methods. That is because the parasitic parameters are always relative to the environment of the interconnects [4]. The advantage of the hierarchical method can't be used in the extraction.…”

Section: Introductionmentioning

confidence: 99%

BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction

Lu¹,

Wang²,

Hong³

Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.

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Abstract-Fast and accurate interconnect parasitic parameter extraction has become increasingly critical for verification and analysis in VLSI today. In this paper, a fast hierarchical extraction approach based on Boundary Element Method (BEM) is presented for 3-D parasitic capacitance computation. Hierarchical partition of the 3-D field creates many parts which are called 3-D BEM blocks. After combining all the 3-D BEM blocks, the capacitance matrix for a given set of nets can be computed by applying the boundary conditions. Numerical results shows that this method performs many times faster than the 3-D field solver, with equal accuracy.

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A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects

Tsai¹,

Hsieh²,

Lu³

et al. 2010

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)

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Accurate and efficient extraction of interconnect circuits for full-chip timing analysis

Cited by 8 publications

References 0 publications

Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

Analysis and justification of a simple, practical 2 1/2-D capacitance extraction methodology

BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction

A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects

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