Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications

Cho, Vincent; Schlessman,; Mukhopadhyay,

doi:10.1109/aspdac.2009.4796582

Cited by 23 publications

(8 citation statements)

References 11 publications

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“…However supply voltage scaling in the memory leads to memory-errors. This happens because voltage scaling increases the sensitivity of the memory elements to the manufacturing variations [9]. As a result, larger number of memory failures occurs at reduced supply voltages and corrupt the stored values of filter coefficients and result in memory errors.…”

Section: B Memory Errormentioning

confidence: 99%

“…Reducing the supply voltage to the SRAM array increases the probability of failure (due to read disturb, access or write failure) of the memory elements [9]. Thus we can reduce the memory errors if we can detect failures in the coefficient memory, and then increase the supply voltage till the failure rate is zero, or at an acceptable value.…”

Section: B Feedback Correction For Memory Errorsmentioning

confidence: 99%

“…Fig. 5 shows the relation between supply voltage (V dd ), the Read margin (data obtained from [9]). From Fig.…”

Section: B Feedback Correction For Memory Errorsmentioning

confidence: 99%

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On improving the algorithmic robustness of a low-power FIR filter

Khire

Mukhopadhyay

2009

2009 IEEE International Conference on Computer Design

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Abstract-Voltage scaling is a promising approach to reduce the power consumption in signal processing circuits. However aggressive voltage scaling can introduce errors in the output signal, thus degrading the algorithmic performance of the circuit. We consider the specific case of the finite impulse response (FIR) filter, and identify two different sources of errors occurring due to voltage scaling: (a) errors introduced because of increased delay along the logic path and (b) errors caused by failures in the memory due to process variations. We design a FIR filter by using a simple feedback based approach to reduce the memory errors and a linear predictor structure for correcting the logic errors. The proposed filter is more robust to both logic and memory errors caused by voltage scaling. The results show a considerable improvement in the output Signal to Noise ratio (at least around 10 dB) for a probability of error (P err ) even as high as 0.5. We also utilize the proposed technique for an image filtering application and observe a considerable improvement in the visual quality of the output image along with an improvement of over 10 dB in the Peak Signal to Noise ratio for P err as high as 0.5.

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Section: B Memory Errormentioning

confidence: 99%

Section: B Feedback Correction For Memory Errorsmentioning

confidence: 99%

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On improving the algorithmic robustness of a low-power FIR filter

Khire

Mukhopadhyay

2009

2009 IEEE International Conference on Computer Design

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“…The method in [11] is a general technique where the memory banks that store MSBs operate at a different voltage level than the ones that store LSBs. This is shown to achieve 45% power reduction with slight degradation in image quality.…”

Section: B Previous Work On Compensating For Sram Errorsmentioning

confidence: 99%

Energy and Quality-Aware Multimedia Signal Processing

Emre

Chakrabarti

2013

IEEE Trans. Multimedia

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Today's mobile devices have to support computation-intensive multimedia applications with a limited energy budget. In this dissertation, we present architecture level and algorithm-level techniques that reduce energy consumption of these devices with minimal impact on system quality.First, we present novel techniques to mitigate the effects of SRAM memory failures in JPEG2000 implementations operating in scaled voltages. We investigate error control coding schemes and propose an unequal error protection scheme tailored for JPEG2000 that reduces overhead without affecting the performance. Furthermore, we propose algorithm-specific techniques for error compensation that exploit the fact that in JPEG2000 the discrete wavelet transform outputs have larger values for low frequency subband coefficients and smaller values for high frequency subband coefficients.Next, we present use of voltage overscaling to reduce the data-path power consumption of JPEG codecs. We propose an algorithm-specific technique which exploits the characteristics of the quantized coefficients after zig-zag scan to mitigate errors introduced by aggressive voltage scaling.Third, we investigate the effect of reducing dynamic range for datapath energy reduction. We analyze the effect of truncation error and propose a scheme that estimates the mean value of the truncation error during the pre-computation stage and compensates for this error. Such a scheme is very effective for reducing the noise power in applications that are dominated by additions and multiplications such as FIR filter and transform computation. We also present a novel sum of absolute difference (SAD) scheme that is based on most significant bit truncation. The proposed scheme exploits the ii fact that most of the absolute difference (AD) calculations result in small values, and most of the large AD values do not contribute to the SAD values of the blocks that are selected. Such a scheme is highly effective in reducing the energy consumption of motion estimation and intra-prediction kernels in video codecs.Finally, we present several hybrid energy-saving techniques based on combination of voltage scaling, computation reduction and dynamic range reduction that further reduce the energy consumption while keeping the performance degradation very low. For instance, a combination of computation reduction and dynamic range reduction for Discrete Cosine Transform shows on average, 33% to 46% reduction in energy consumption while incurring only 0.5dB to 1.5dB loss in PSNR.

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“…, dynamic range adjustment of data-path units or truncation [6][7][8][9][10] and voltage scaling [11][12][13][14][15][16][17][18]. Recently approximate circuits have been proposed in [19][20][21][22][23][24][25][26][27] which also reduce area, latency and power.…”

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confidence: 99%

Image processing using approximate datapath units

Vasudevan

Chakrabarti

2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this work, we present approximate adders and multipliers to reduce data-path complexity of specialized hardware for various image processing systems. These approximate circuits have a lower area, latency and power consumption compared to their accurate counterparts and produce fairly accurate results. We build upon the work on approximate adders and multipliers presented in [23] and [24]. First, we show how choice of algorithm and parallel adder design can be used to implement 2D Discrete Cosine Transform (DCT) algorithm with good performance but low area. Our implementation of the 2D DCT has comparable PSNR performance with respect to the algorithm presented in [23] with ~35-50% reduction in area. Next, we use the approximate 2x2 multiplier presented in [24] to implement parallel approximate multipliers. We demonstrate that if some of the 2x2 multipliers in the design of the parallel multiplier are accurate, the accuracy of the multiplier improves significantly, especially when two large numbers are multiplied. We choose Gaussian FIR Filter and Fast Fourier Transform (FFT) algorithms to illustrate the efficacy of our proposed approximate multiplier. We show that application of the proposed approximate multiplier improves the PSNR performance of 32x32 FFT implementation by 4.7 dB compared to the implementation using the approximate multiplier described in [24]. We also implement a state-of-the-art image enlargement algorithm, namely Segment Adaptive Gradient Angle (SAGA) [29], in hardware. The algorithm is mapped to pipelined hardware blocks and we synthesized the design using 90 nm technology. We show that a 64x64 image can be processed in 496.48 µs when clocked at 100 MHz. The average PSNR performance of our implementation using accurate parallel adders and multipliers i is 31.33 dB and that using approximate parallel adders and multipliers is 30.86 dB, when evaluated against the original image. The PSNR performance of both designs is comparable to the performance of the double precision floating point MATLAB implementation of the algorithm. This work is also affectionately dedicated to the six different computers that were used to complete this work.

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Accuracy-aware SRAM: A reconfigurable low power SRAM architecture for mobile multimedia applications

Cited by 23 publications

References 11 publications

On improving the algorithmic robustness of a low-power FIR filter

On improving the algorithmic robustness of a low-power FIR filter

Energy and Quality-Aware Multimedia Signal Processing

Image processing using approximate datapath units

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