Acceleration of the L4/Fiasco microkernel using scratchpad memory

2009 International Symposium on System-on-Chip

Showk

Hessel

et al. 2009

Abstract-In this paper we present detailed profiling results and identify the time critical algorithms of the Long Term Evolution (LTE) layer 2 (L2) protocol processing on an ARM based mobile hardware platform. Furthermore, we investigate the applicability of a single ARM processor combined with a traditional hardware acceleration concept for the significantly increased computational demands in LTE and future mobile devices. A virtual prototyping approach is adopted in order to simulate a state-of-the-art mobile phone platform which is based on an ARM1176 core. Moreover a physical layer and base station emulator is implemented that allows for protocol investigations on transport block level at different transmission conditions . By simulating LTE data rates of 100 Mbit/s and beyond, we measure the execution times in a protocol stack model which is compliant to 3GPP Rel.8 specifications and comprises the most processing intensive downlink (DL) part of the LTE L2 data plane. We show that the computing power of a single embedded processor at reasonable clock frequencies is not enough to cope with the L2 requirements of next generation mobile devices. Thereby, Robust Header Compression (ROHC) processing is identified as the major time critical software algorithm, demanding half of the entire L2 DL execution time. Finally, we illustrate that a conventional hardware acceleration approach for the encryption algorithms fails to offer the performance required by LTE and future mobile phones.

Section: Resultsmentioning

confidence: 99%

“…Execution time measurements of the complete data plane of the LTE DL protocol stack model are obtained in the deciphering enabled mode. Moreover, the system is simulated at different data and instruction cache sizes (8,16, 32 and 64 kB) for the ARM1176 processor.…”

Section: Resultsmentioning

confidence: 99%

Performance analysis of LTE protocol processing on an ARM based mobile platform

2009 International Symposium on System-on-Chip

Showk

Hessel

et al. 2009

“…The core of the hardware platform is an ARM1176 embedded processor [10] representing a common choice for state-of-the-art mobile devices [11]. It provides 64-bit and 32-bit AMBA AXI bus interfaces [12] connecting to the instruction and data buses and a peripheral bus, respectively.…”

Section: A Hardware Platformmentioning

confidence: 99%

Optimizing the Processing Performance of a Smart DMA Controller for LTE Terminals

2010 IEEE 16th International Conference on Embedded and Real-Time Computing Systems and Applications

Hessel

Traboulsi

et al. 2010

Abstract-In this paper we present an extended and optimized version of a smart Direct Memory Access (sDMA) controller supporting different on-the-fly protocol stack acceleration concepts for Long Term Evolution (LTE) mobile terminals. In addition to the downlink processing, we analyse different on-the-fly hardware acceleration modes for the uplink protocol stack processing in layer 2 (L2). Moreover, the system performance is further improved by adopting parallelization methods. The efficiency of on-the-fly hardware acceleration is proved by comparing the transport block processing times to those achieved with a conventional hardware accelerator. Therefore, a cycle approximate virtual prototype of a state-of-the-art mobile phone platform based on an ARM1176 processor is simulated at LTE-Advanced data rates of up to 1 Gbit/s. In uplink direction, we are able to reduce the complexity in the sDMA controller and simultaneously improve the processing performance in the mobile platform. This is realized by intelligent hardware/software partitioning and an optimized descriptor format. Furthermore, a significant optimization (up to 13 %) of the system performance in a mobile device is achieved by adopting parallelized on-the-fly hardware acceleration modes. We show how the sDMA controller clearly outperforms the traditional approach by reaching speedups of up to 35 % and 66 % for the transport block processing times in uplink and downlink directions, respectively.

“…In the first concept, scratchpad memories (SPMs) are involved which deliver a speedup of the execution times and better energy efficiency [4], [5]. Compared to hardware controlled caches, this software controlled alternative is also located close to the processor and provides fast access times as well.…”

Section: Introductionmentioning

confidence: 99%

Exploration of energy efficient acceleration concepts for the ROHCv2 in LTE handsets

2011 6th IEEE International Symposium on Industrial and Embedded Systems

Traboulsi

Bruns

et al. 2011

In this paper, we present different acceleration concepts for the Robust Header Compression version 2 (ROHCv2) algorithms in Long Term Evolution (LTE) handsets. First, we explore the potential performance improvements and energy savings by adopting scratchpad memories at various sizes. Second, dedicated hardware accelerators with different data transfer modes are compared in terms of processing speed and energy efficiency on system level. By applying a virtual prototyping methodology with a proprietary filter module, we are able to investigate these two approaches within a state-of-the-art ARM based mobile phone platform at real software loads. Additionally, combined measurements of the execution time together with an estimation of the energy, that is consumed in the memory and the bus architecture, are performed. With reasonably dimensioned scratchpad memories (16 kB for instructions and data respectively), maximum speedups and energy savings both of approximately 60 % are achieved depending on the cache sizes in the embedded processor. Even better performance, especially in combination with big caches, is reached with a dedicated ROHCv2 hardware accelerator supporting the processing of several packets at once in a so called list mode. Compared to the pure software case, the execution time and the energy consumption are both improved by up to 80 % at small caches and still amount to more than 40 % and almost 30 % at big caches, respectively.