Accelerating the compaction of test sequences in sequential circuits through problem size reduction

Dimopoulos, Michael G.; Linardis, Panagiotis

doi:10.1109/tcad.2003.818118

Cited by 8 publications

(4 citation statements)

References 20 publications

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“…Flowchart of Backward Compaction through this method. An alternative is described in [7], wherein an exact method (i.e. not an approximation algorithm) that computes the optimal solution using a set of problem-size reduction rules and a branch-and-bound algorithm is proposed.…”

Section: B Selecting Among Independent Test Sequencesmentioning

confidence: 99%

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Spin-Pac

Shi

Makris

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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SPIN-PAC is a static test compaction method for Speed-Independent circuits. We demonstrate how the test sets can be compacted by combining multiple consecutive test vectors within a test sequence into a vector pair of higher Hamming distance, and by eliminating or pruning independent test sequences. We discuss the exponential nature of optimally solving this problem, we propose an efficient algorithm to approximate it, and we evaluate its performance through experiments.

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Section: B Selecting Among Independent Test Sequencesmentioning

confidence: 99%

“…SPIN-PAC addresses these issues by employing the method proposed in [8]. The problem is modelled as an integer linear program (ILP), the polynomial time reduction rules of [7] are applied, and the remainder problem is approximated through linear program relaxation and randomized rounding [9].…”

Section: B Selecting Among Independent Test Sequencesmentioning

confidence: 99%

Spin-Pac

Shi

Makris

2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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“…In general, fault coverage is computed by sequential fault simulation of the transparent-scan sequence. This view of the test application process does not require any modifications to the scan design or the design of the circuit.. test data compression that consists of test vector compression on the input side and response compaction on the output side [3]- [4]. Test vector compression has been an active area of research.…”

Section: Introductionmentioning

confidence: 99%

Test Compaction of Logic Blocks by using Fault Identification Method

Vardhan¹,

Sathiskumar²

2015

International Journal of Advanced Research in Computer and Comm

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An arbitrary design implemented into a field-programmable gate array (FPGA). FPGA contains many logical blocks. Fault equivalence and fault dominance method are used to detect the fault with minimum time period. An approach provides transparent scan to share tests among different logic blocks whose primary inputs and outputs are included in scan chains even if the blocks have different numbers of state variables. The transparent-scan sequences based on tests for one logic block could detect faults in other logic blocks, with different numbers of state variable. It uses n number of test configuration instead of 2 n number of test configuration by test code algorithm. Transparent scan enhances the ability to produce a compact test set for a group of logic blocks. The procedure obtains a set of transparent-scan sequences for a group of logic blocks from compacted test sets for the logic blocks in the group. From this set, it chooses a subset that finds all the target faults, which are propagated by the complete set by using Modelsim and area is obtained by using the XILINX ISE 8.1 software.

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“…• ο SeqCompact παράγει πολύ γρήγορα (χρειάστηκε µερικά δευτερόλεπτα για όλα τα παραδείγµατα) συµπιεσµένες ακολουθίες (σε όλα τα παραδείγµατα βρήκε τις βέλτιστες λύσεις) ενώ η συµπεριφορά του σε µεγάλα παραδείγµατα και σύνολα ελέγχου είναι ικανοποιητική Από αυτό το κεφάλαιο προέκυψαν οι ακόλουθες δηµοσιεύεις: [49,50,51,53,56].…”

Section: απόδειξηunclassified

Μέθοδοι Ελέγχου Ολοκληρωμένων Ψηφιακών Κυκλωμάτων

Dimopoulos¹,

Δημόπουλος²

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ISBN «Η έγκριση της παρούσης ∆ιδακτορικής ∆ιατριβής από το Τµήµα Πληροφορικής του Αριστοτελείου Πανεπιστηµίου Θεσσαλονίκης δεν υποδηλώνει αποδοχή των γνωµών του συγγραφέως» (Ν. 5343/1932, άρθρο 202, παρ. 2) Αφιερώνεται στους γονείς µου και στην αδερφή µου Ελευθερία VI XII XIII Επιστηµονικές ∆ηµοσιεύσεις Α) ∆ηµοσιεύσεις σε περιοδικά

show abstract

Accelerating the compaction of test sequences in sequential circuits through problem size reduction

Cited by 8 publications

References 20 publications

Spin-Pac

Spin-Pac

Test Compaction of Logic Blocks by using Fault Identification Method

Μέθοδοι Ελέγχου Ολοκληρωμένων Ψηφιακών Κυκλωμάτων

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