Spin-Pac

Shi, Feng; Makris, Yiorgos

doi:10.1145/1120725.1120746

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05 2005

DOI: 10.1145/1120725.1120746

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Spin-Pac

Feng Shi

Yiorgos Makris

Abstract: SPIN-PAC is a static test compaction method for Speed-Independent circuits. We demonstrate how the test sets can be compacted by combining multiple consecutive test vectors within a test sequence into a vector pair of higher Hamming distance, and by eliminating or pruning independent test sequences. We discuss the exponential nature of optimally solving this problem, we propose an efficient algorithm to approximate it, and we evaluate its performance through experiments.

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Cited by 2 publications

References 13 publications

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A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines

Shi

Makris

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

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We discuss a transistor-level test methodology for C 2 MOS asynchronous pipelines. Unlike their static CMOS counterparts, wherein testing for stuck-at faults and compliance to a few timing constraints typically suffices, dynamic asynchronous pipelines present new challenges which require more elaborate test solutions. More specifically, many gate-level input/output stuck-at faults of a static pipeline style translate into transistorlevel stuck-open/stuck-short faults in the dynamic C 2 MOS version. Therefore, test methods for transistor-level faults are required for dynamic asynchronous pipelines. To this end, we propose a methodology for testing both gate-level stuckat faults and transistor-level stuck-open/stuck-short faults in C 2 MOS pipelines. The proposed method does not employ additional hardware and is capable of detecting both gate-level and transistor-level faults, as we demonstrate on the C 2 MOS version of MOUSETRAP.

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A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines

Shi

Makris

12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'06)

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Test generation for ultra-high-speed asynchronous pipelines

Shi

Makris

Nowick

et al.

IEEE International Conference on Test, 2005.

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We propose a methodology for testing ultra-high-speed asynchronous pipelines, the latest and most promising asynchronous circuit design style. Unlike traditional delayinsensitive asynchronous micro-pipelines, which use slow capture-pass latches, these circuits employ aggressive handshaking protocols and transparent latches between fine-grain pipeline stages, in order to achieve high performance. Their functional robustness, however, relies on certain timing constraints that need to be satisfied. As a result, these circuits are no longer delay-insensitive, which means that stuck-at faults will not always lead to pipeline stalling. In addition, delay faults may result in violation of these timing constraints, thus affecting not only performance, as in delay-insensitive micro-pipelines, but also functional correctness. To address these new challenges, we develop a test method for both stuck-at and timing constraint violation faults in fine-grain ultra-high-speed asynchronous pipelines. The efficiency of the proposed method is demonstrated on MOUSETRAP, a recently developed pipeline for high-speed applications.

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Spin-Pac

Cited by 2 publications

References 13 publications

A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines

A Transistor-Level Test Strategy for C^2MOS MOUSETRAP Asynchronous Pipelines

Test generation for ultra-high-speed asynchronous pipelines

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