Accelerating concurrent hardware design with behavioural modelling and system simulation

Silburt, A.L.; Perryman, Ian; Bergeron, Janick; Nichols, Stacy William; Dufresne, Mario; Ward, Greg

doi:10.1145/217474.217582

Cited by 8 publications

(2 citation statements)

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“…Initially, the testbenches were developed using the behavioural model and then as the RTL stabilized, both platforms were used for writing testbenches. [1] Near the end of the ASIC testbench effort, system testbench development began in parallel using the behavioural models. The objective of these simulations was to prove the interfaces between ASICs and verify the protocol error conditions.…”

Section: Verification Methodologymentioning

confidence: 99%

Functional verification of large ASICs

Evans

Silburt

Vrckovnik

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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This paper describes the functional verification effort during a specific hardware development program that included three of the largest ASICs designed at Nortel. These devices marked a transition point in methodology as verification took front and centre on the critical path of the ASIC schedule. Both the simulation and emulation strategies are presented. The simulation methodology introduced new techniques such as ASIC sub-system level behavioural modeling, large multi-chip simulations, and random pattern simulations. The emulation strategy was based on a plan that consisted of integrating parts of the real software on the emulated system. This paper describes how these technologies were deployed, analyzes the bugs that were found and highlights the bottlenecks in functional verification as systems become more complex.

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Section: Verification Methodologymentioning

confidence: 99%

Functional verification of large ASICs

Evans

Silburt

Vrckovnik

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

Self Cite

View full text Add to dashboard Cite

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“…To solve this problem, the scale must first be reduced by applying policy 1, 2, and 3 because increases in the scale of the target lead to reduced simulation speed. It has also been reported that the functions can be verified on a per-cycle (stepwise) basis without detailed timing verification and that improvements in speed can be achieved by using a high-level cycle-based simulator that is able to verify the behavioral model directly without gate-level analysis or RTL simulation [3], and thus policy 4 must be augmented by an additional policy: · POLICY 6: Use a high-level stepwise simulator.…”

Section: Issue 2: the Simulation Speed Is Lowmentioning

confidence: 99%

Hardware/software co-simulation focusing on functional verification of large-scale ASICs

et al. 1999

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Despite the increasing scale of ASICs and the increasing complexity of embedded systems in which they are incorporated, developers continue to expect reductions in development time. HW/SW co‐simulation has been put forward as a potential means of meeting this demand since it allows inconsistencies between components such as ASICs and software to be spotted before a hardware prototype has been completed, and since it is also an efficient tool for the functional verification of ASICs, a process that takes up a large part of their development time. However, it has not been widely used for the functional verification of real systems due to various problems, such as the high development cost of simulation environments, the slow simulation speed, and the limited scope of this verification. This paper proposes a method that solves these problems yet is still able to offer the basic advantages of HW/SW co‐simulation, such as the ability to efficiently verify ASIC functions and the interfaces between components. By applying the proposed method to a system under development we were also able to construct a complete simulation environment in just two weeks with one‐eighth of the amount of code needed for ASIC development. We have also confirmed that, compared with the logical simulation of ASICs on their own, the proposed method approximately doubles the verifiable scope, can reduce the amount of data statements for verification by a factor of 150, can detect 18 types of fault such as inconsistencies in the interfaces between components, and yet it only results in a 7% drop in simulation speed. © 1999 Scripta Technica, Syst Comp Jpn, 30(1): 43–59, 1999

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Methodology for ATM-cell processing system design

Muller

Kogel²,

Post³

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

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Accelerating concurrent hardware design with behavioural modelling and system simulation

Cited by 8 publications

References 0 publications

Functional verification of large ASICs

Functional verification of large ASICs

Hardware/software co-simulation focusing on functional verification of large-scale ASICs

Methodology for ATM-cell processing system design

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