Methodology for ATM-cell processing system design

Muller, A.; Kogel, Tim; Post, Guido

doi:10.1109/asic.1999.806479

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Hw/sw Codesign and Traditional Design Space Exploration1

Early Grace/lisa Co-simulation (Aachen University)1

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Cited by 3 publications

(2 citation statements)

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“…Since the combined execution limited the simulation speed of such approaches, the GRACE++ methodology [107,108], among others, targeted abstraction levels higher than RTL to achieve increased simulation speed. Yet, modeling was still cycle and pin accurate.…”

Section: Hw/sw Codesign and Traditional Design Space Explorationmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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Section: Hw/sw Codesign and Traditional Design Space Explorationmentioning

confidence: 99%

Multiprocessor Systems on Chip

Kempf¹,

Ascheid²,

Leupers³

2011

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“…LISA processor simulators [23] applying fast compiled simulation were coupled to GRACE hardware models [24], which allow higher simulation speed by being modeled on a higher level of abstraction than Register-Transfer-Level (RTL). However, the interface protocol was modeled pin and cycle accurately only, and the coupling could not be generated automatically yet.…”

Section: Early Grace/lisa Co-simulation (Aachen University)mentioning

confidence: 99%

Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms

Wieferink¹,

Meyr²,

Leupers³

2008

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Acceleration of DAB chipset development by deployment of a real-time rapid prototyping approach based on behavioral synthesis

Speitel

Schlicht

Leyh

2001

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

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The development of a new digital communication system has the twofold goal to achieve all traditional requirements from the end user prospective and to offer a huge potential of additional services compared with existing analog systems. The extremely demanding time frame for the introduction of such a system requires a development approach reducing the design risk to a minimum especially for the end user receivers. As integral parts of the terminal the digital baseband processor is one of the most challenging receiver components in terms of development and validation effort. The complexiv of the ASIC design with initially estimated 500,000 to 1,000,000 gate equivalents has driven the deployment of a real-time prototyping system. To assure real-time and identical functionality on both FPGA prototype and ASIC behavioral synthesis was used for timing-critical and computationally intensive building blocks. The design and validation methodology was successfully implemented. The ASIC will be introduced in the first generation of mobile radio receivers foK digital audio broadcasting in the United States.

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Methodology for ATM-cell processing system design

Cited by 3 publications

References 5 publications

Multiprocessor Systems on Chip

Multiprocessor Systems on Chip

Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms

Acceleration of DAB chipset development by deployment of a real-time rapid prototyping approach based on behavioral synthesis

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