Accelerated analysis of Boolean gene regulatory networks

Purandare, Mitra; Polig, Raphael; Hagleitner, Christoph

doi:10.23919/fpl.2017.8056778

Cited by 6 publications

(8 citation statements)

References 21 publications

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“…Já nas abordagens propostas com FPGA, o maior gargaloé o tempo de compilação e a complexidade do projeto queé específico para cada rede [Purandare et al 2017, Pournara et al 2005, da Silva et al 2017.…”

Section: Trabalhos Relacionadosunclassified

“…Este trabalho difere dos anteriores ao explorar três arquiteturas para implementação da operação básica, o cálculo do próximo estado. Trabalhos futuros poderão avaliar o desempenho para execução de algoritmos que envolverão a evolução dos estados [Purandare et al 2017, da Silva et al 2017, Trinh et al 2014, Borelli et al 2013.…”

Section: Trabalhos Relacionadosunclassified

“…Buscando implementações com desempenho e eficiência energética, este trabalho propõe avaliar arquiteturas multi-core, GPU e FPGA para implementação eficiente da avaliação dos estados. Apesar da eficiência demonstrada pelos FPGAs para avaliação de redes de genes [Purandare et al 2017, Pournara et al 2005, da Silva et al 2017, o tempo de compilação/sínteseé longo (minutos a horas) e a complexidade das ferramentas de projeto restringem o uso de FPGAs. Neste trabalho, apresentamos uma alternativa simples com uma camada virtual sobre um FPGA comercial semelhanteà abordagem proposta em [Ferreira and Vendramini 2010], transparente para o usuário que não necessita ter nenhum conhecimento de FPGAs e suas ferramentas.…”

Section: Introductionunclassified

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Simulação de Redes Reguladoras de Genes com Lógica Booleana e Limiar em Plataformas Alto Desempenho

Rosa

Baranda

Canesche

et al. 2019

Anais Do XX Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2019)

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As redes reguladoras de genes são modelos baseados em grafos muito utilizadas para estudar o comportamento de células, processos de diferenciação celular ou tratamento e evolução de doenças. Uma rede pode ser implementada por um grafo com equações booleanas. Os algoritmos usados nas simulações das redes avaliam estas equações várias vezes ao longo da execução. Este artigo propõe um estudo das implementações em CPU, GPU e FPGA da operação básica que é o cálculo do próximo estado. Exploramos as técnicas de vetorização e paralelização com AVX e OpenMP para os processadores e uma nova arquitetura dinâmica é proposta para simplificar o uso das soluções com FPGA. Além do modelo booleano, mostramos como as redes podem ser transformadas em equações com somas de peso e limiares. Finalmente, 16 redes biológicas usados na literatura foram avaliadas, onde as implementações em CPU com OMP apresentaram uma aceleração de 3x em comparação com a CPU, as implementações em GPU foram em média 57,3x mais rápidas que a CPU e finalmente as implementações em FPGA foram em média 86,7x mais rápidas que a CPU. ∗

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Section: Trabalhos Relacionadosunclassified

Section: Introductionunclassified

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Simulação de Redes Reguladoras de Genes com Lógica Booleana e Limiar em Plataformas Alto Desempenho

Rosa

Baranda

Canesche

et al. 2019

Anais Do XX Simpósio Em Sistemas Computacionais De Alto Desempenho (SSCAD 2019)

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“…A particular challenge is simulating the dynamics of Gene Regulatory Networks (GRNs), which could be used for a variety of pathological settings, including genetic tumor syndromes, cancer, and obesity. Previous works propose specific FPGA accelerators to speed up GRN computations in addition to traditional CPUs. We have chosen this case study in particular because it allows us to present three different aspects of the ADD framework.…”

Section: Performance Metrics and Analysismentioning

confidence: 99%

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Penha

Silva

et al. 2018

Concurrency and Computation

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Summary Dataflow‐based FPGA accelerators have become a promising alternative to deliver energy‐efficient high‐performance computing. However, FPGA programming is still a challenge. This paper presents Accelerator Design and Deploy (ADD), a high‐level framework to specify, to simulate, and to implement dataflow accelerators for streaming applications. The framework includes an open dataflow operator library, and templates are provided to easily design new operators. The framework also provides a high‐level and an accurate simulation at circuit level with short execution times. Moreover, ADD provides software and hardware APIs to simplify the integration process, extending the benefits of portability from low‐cost FPGA boards to high performance datacenter FPGA platforms. Our framework supports coupling with high‐level programming languages, and it has been validated on two FPGA platforms: the Intel high‐performance CPU‐FPGA heterogeneous computing platform and an educational FPGA kit. We show that our simple approach presents competitive performance, both in time and energy, when compared to multi‐core and GPU accelerators.

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“…By performing slight modifications, the proposed method can be used to simulate arbitrary Boolean networks, which opens many interesting perspectives. While there are several works on FPGA simulation of Boolean networks, e.g., [27,28,29], our article differs from them by highlighting the theoretical link between the model of Boolean networks and sequential switching circuits, hence implementing the corresponding simulation in most efficient way.…”

Section: Introductionmentioning

confidence: 96%

Reaction Systems and Synchronous Digital Circuits

et al. 2019

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A reaction system is a modeling framework for investigating the functioning of the living cell, focused on capturing cause–effect relationships in biochemical environments. Biochemical processes in this framework are seen to interact with each other by producing the ingredients enabling and/or inhibiting other reactions. They can also be influenced by the environment seen as a systematic driver of the processes through the ingredients brought into the cellular environment. In this paper, the first attempt is made to implement reaction systems in the hardware. We first show a tight relation between reaction systems and synchronous digital circuits, generally used for digital electronics design. We describe the algorithms allowing us to translate one model to the other one, while keeping the same behavior and similar size. We also develop a compiler translating a reaction systems description into hardware circuit description using field-programming gate arrays (FPGA) technology, leading to high performance, hardware-based simulations of reaction systems. This work also opens a novel interesting perspective of analyzing the behavior of biological systems using established industrial tools from electronic circuits design.

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Accelerated analysis of Boolean gene regulatory networks

Cited by 6 publications

References 21 publications

Simulação de Redes Reguladoras de Genes com Lógica Booleana e Limiar em Plataformas Alto Desempenho

Simulação de Redes Reguladoras de Genes com Lógica Booleana e Limiar em Plataformas Alto Desempenho

ADD: Accelerator Design and Deploy ‐ A tool for FPGA high‐performance dataflow computing

Reaction Systems and Synchronous Digital Circuits

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