AC NBTI studied in the 1 Hz -- 2 GHz range on dedicated on-chip CMOS circuits

Abstract

We describe on-chip circuits specially designed and fabricated for the purpose of measuring the effect of AC NBTI on an individual, well-defined device in the wide frequency range on a single wafer. The circuits are designed to allow measurements in multiple modes, specifically, DC and AC NBTI (both interrupted and on-the-fly), on a single pFET and on a CMOS inverter, as well as charge-pumping characterization of the stressed pFET. The results indicate that AC NBTI is independent of the frequency in the 1 Hz -2 GHz range. The voltage and stress time acceleration is observed to be identical for both AC and DC NBTI stress.

A Finite-Oxide Thickness-Based Analytical Model for Negative Bias Temperature Instability

“…This property is known as frequency independence. Although several differing experimental results have been observed, recent experiments have shown that this holds good over the 1Hz-1GHz bandwidth [38], which seconds the analytical findings in [16]. However, as we move closer to DC, some form of frequency dependence is expected.…”

“…Thus, on the basis of experimental data from [38], and the trend seen in Fig. 21, we conclude that the interface trap count determined for τ = 1s, asymptotically equals the number for a case where τ = 1ns, over t life , where t life is the lifetime of the circuit, and is assumed to be 10 years of operation:…”

“…5) The model must predict some form of frequency independence, i.e., the number of interface traps generated must approximately be the same asymptotically, irrespective of the frequency of operation. Although, the exact range of frequencies over which this phenomenon holds good is still not very clear, some form of frequency independence is widely observed in the 1Hz -1MHz range [4], [34] and has recently been shown to exist over the entire range of 1Hz -2GHz in [38].…”

Modelling and experimental verification of the impact of negative bias temperature instability on CMOS inverter

“…Two types of noise margin can be differentiated; low noise margin (NML) and high noise margin (NMH), which correspond with the minimum noise level signal to switch the CMOS inverter from low to high and from high to low, respectively. The NML and NMH are defined by (3) where V IL , V OL , V OH , V IH are obtained when the slope of VTC equals −1 (Fig. 3).…”

“…The NBTI effect on static and dynamic stress has been also reported. These investigations show that the voltage threshold shift (∆V th ) under dynamic stress is almost half of DC case, due to the recovery properties of NBTI [3]. At circuit level, the NBTI effects have not been deeply investigated.…”