AAS-Maps: Aging-aware sensitivity-maps for reliability driven analog circuit design

Hellwege, Nico; Heidmann, Nils; Peters-Drolshagen, Dagmar; Paul, Steffen

doi:10.1109/irps.2014.6860672

Cited by 5 publications

(2 citation statements)

References 11 publications

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“…Degradation due to BTI and HCD alters the operating point of a MOS transistor and therefore changes the output characteristics of whole circuits [10] [17]. The change in the transistor parameters, , which shall be written as d, is dependent on the degradation time t age .…”

Section: B Degradation and Operating Pointmentioning

confidence: 99%

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Hellwege

Heidmann

Erstling

et al. 2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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In this paper we present a tool based approach for an aging-aware design method. Extending the gm /I D sizing method by operating point-dependent degradation caused by BTI and HCD enables an innovative design flow. This design flow considers performance characteristics for a fresh circuit and also those of a degraded circuit at design time. Once the degradation from a single transistor is computed, the GMID-Tool does not need any further SPICE or aging simulation. The impact of the change in design methodology is shown for a typical differential amplifier structure.

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Section: B Degradation and Operating Pointmentioning

confidence: 99%

An aging-aware transistor sizing tool regarding BTI and HCD degradation modes

Hellwege

Heidmann

Erstling

et al. 2015

2015 22nd International Conference Mixed Design of Integrated Circuits &Amp; Systems (MIXDES)

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“…In [1] the gm /ID design method is extended by operatingpoint dependent degradation. This extension provides information about performances degradation with respect to circuit aging during design time.…”

Section: Introductionmentioning

confidence: 99%

NBTI and HCD aware behavioral models for reliability analysis of analog CMOS circuits

Heidmann

Hellwege

Paul

et al. 2015

2015 IEEE International Reliability Physics Symposium

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For safety-critical applications with long operational lifetimes the analysis of aging aspects caused by NBTI and HCD is moving into the focus of the designer. The increasing complexity of modern analog and mixed-signal circuits makes a reliability analysis on transistor level for complex systems quite challenging. In this paper we present a method using BoxBehnken Designs and Response Surface Modeling with exponential function interpolation. This approach enables accelerated reliability analysis on system level. A tool is introduced to support the behavioral model generation process. The derived model includes information on degradation and process variations. The method is demonstrated for a current-mirror and a CS amplifier to quantify the degradation influence. The accuracy of the behavioral models and the age-dependent yield of the circuits is determined.

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