AADL modeling and analysis of hierarchical schedulers

Singhoff, Frank; Plantec, Alain

doi:10.1145/1315580.1315593

Cited by 32 publications

(16 citation statements)

References 28 publications

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“…In this paper, we are also interested in code synthesis, as well as analysis (using task automata). This is similar to [20], where the authors show how modeling and schedulability analysis of two-level hierarchical scheduling, with timed automata, can be accomplished in the simulation tool Cheddar.…”

Section: B Code Synthesismentioning

confidence: 53%

Prototyping Hierarchically Scheduled Systems Using Task Automata and TIMES

Åsberg

Nolte

Pettersson

2010

2010 5th International Conference on Embedded and Multimedia Computing

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In hierarchical scheduling, a system is organized into multiple levels of individually scheduled subsystems (hierarchical scheduling tree), which provides several benefits for developers including possibilities for parallel development of subsystems. In this paper, we study how the model of task automata and the Times tool can be applied to provide support for rapid and early prototyping of hierarchically scheduled embedded systems.As a main result, we show how a single node, in an arbitrary level in a hierarchical scheduling tree (scheduled with fixedpriority preemptive scheduling), can easily be analyzed in Times by replacing all interfering nodes with a small set of higher priority (dummy) tasks. We show with an algorithm how these dummy tasks are generated (including task-parameters such as period, offset etc.). Further, we generate executable source code, with the Times code-generator, that emulates the scheduling environment (with our dummy tasks), i.e., the hierarchical scheduling tree and all of its preemptions, of a small example system. Yet another contribution is that we transform the generated (brickOS) source code to run on an industrial oriented platform (VxWorks), and conduct an performance evaluation.

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Section: B Code Synthesismentioning

confidence: 53%

Prototyping Hierarchically Scheduled Systems Using Task Automata and TIMES

Åsberg

Nolte

Pettersson

2010

2010 5th International Conference on Embedded and Multimedia Computing

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“…Formal specification of the ARINC 653 architecture and components has been developed using Circus language [20], AADL (Architecture Analysis and Design Language) [21][22][23], and PROMELA in the SPIN model checker [24]. Since the ARINC 653 services are not the emphasis of these works, only a small part of services are modelled.…”

Section: Related Workmentioning

confidence: 99%

Formal Specification and Analysis of Partitioning Operating Systems by Integrating Ontology and Refinement

Zhao

Sanán

Zhang

et al. 2016

IEEE Trans. Ind. Inf.

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Partitioning Operating Systems (POSs) have been widely applied in safety-critical domains from aerospace to automotive. In order to improve the safety and certification process of POSs, the ARINC 653 standard has been developed and complied with by the mainstream POSs. Rigorous formalization of ARINC 653 can reveal hidden errors in this standard and provide a necessary foundation for formal verification of POSs and ARINC 653 applications. For the purpose of reusability and efficiency, a novel methodology by integrating ontology and refinement is proposed to formally specify and analyze POSs in this paper. An ontology of POSs is developed as an intermediate model between informal descriptions of ARINC 653 and the formal specification in Event-B. A semi-automatic translation from the ontology and ARINC 653 into Event-B is implemented, which leads to a complete Event-B specification for ARINC 653 compliant POSs. During the formal analysis, six hidden errors in ARINC 653 have been discovered and fixed in the Event-B specification. We also validate the existence of these errors in two open-source POSs, i.e., XtratuM and POK. By introducing the ontology, the degree of automatic verification of the Event-B specification reaches a higher level.

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“…two tasks communicating with sampling or queuing port must be put in different partitions. For the moment, we only implement manual task allocation according to the integrator's experience and check the task allocation correctness by hierarchical scheduling simulation proposed in [8] for each integrated model. In future, we will implement an automatic task allocation optimism algorithm to compute allocation solution to achieve the least communication cost and system response time in a schedulable condition.…”

Section: Model Integration and Analysismentioning

confidence: 99%

“…The two partitions are respectively binding to a separate memory to enforce spatial partitioning and a unique virtual processor to implement temporal partitioning by each allocated 40ms and 20ms scheduling window in a 60ms major frame. The integrated model is then verified schedulable with the Cheddar tool [8]. Finally, the RT-Java partition initialization and task behavior code, as well as XML configuration code can be generated automatically from this verified model.…”

Section: Case Studymentioning

confidence: 99%

An Automatic Development Process for Integrated Modular Avionics Software

Wang¹,

Ma²

2013

JNW

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With the ever-growing avionics functions, the modern avionics architecture is evolving from traditional federated architecture to Integrated Modular Avionics (IMA). ARINC653 is a major industry standard to support partitioning concept introduced in IMA to achieve security isolation between avionics functions with different criticalities. To decrease the complexity and improve the reliability of the design and implementation of IMA-based avionics software, this paper proposes an automatic development process based on Architecture Analysis & Design Language. An automatic model transformation approach from domain-specific models to platform-specific ARINC653 models and safety-critical ARINC653-compliant code generation technology are respectively presented during this process. A simplified multi-task flight application as a case study with preliminary experiment result is given to show the validity of this process.

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AADL modeling and analysis of hierarchical schedulers

Cited by 32 publications

References 28 publications

Prototyping Hierarchically Scheduled Systems Using Task Automata and TIMES

Prototyping Hierarchically Scheduled Systems Using Task Automata and TIMES

Formal Specification and Analysis of Partitioning Operating Systems by Integrating Ontology and Refinement

An Automatic Development Process for Integrated Modular Avionics Software

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