A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

Sandner, C.; Derksen, S.; Draxelmayr, D.; Ek, Staffan; Filimon, V.; Leach, G.; Marsili, S.; Matveev, D. A.; Mertens, K.; Michl, Florian; Paule, H.; Punzenberger, M.; Reindl, Christian; Salerno, R.; Tiebout, M.; Wiesbauer, A.; Winter, Ian M.; Zhang, Zisan

doi:10.1109/jssc.2006.884804

Cited by 64 publications

(24 citation statements)

References 9 publications

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“…Even if such a high speed can be achieved in future with more advanced VLSI technologies, the DAC remains the speed bottleneck [28]. One solution to this problem is to use a fixed high frequency clock from a PLL, and utilize SSB mixers to add or subtract the lower frequency clock generated by the DDS [29]. In this architecture, the sinusoidal low frequency IQ signals are stored in a read-only memory (ROM) look-up table.…”

Section: Direct Digital Synthesismentioning

confidence: 99%

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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Sweden Cover image:The cover image illustrates a sine-shaped "wordle" of the thesis.Printed by LiU-Tryck, Linköping University Linköping, Sweden, 2014 iii AbstractEver increasing demand for high speed transmission of large data between the electronic devices within a wireless personal area network has been motivating the development of the appropriate wireless standards. Ultra-wideband (UWB) communication employs the unlicensed frequency spectrum of 3.1 -10.6 GHz and utilizes a low average transmit power to offer the potential for high data rates in short range wireless links. WiMedia specification for UWB employs a frequency hopping scheme which requires a very fast hopping speed of 9.47 ns. Also, the strong interferers from the coexisting wireless technologies put stringent requirements on synthesizer's sideband spurs. Satisfying such challenging requirements using conventional frequency synthesis approaches is impractical and demands for exploration, analysis and design of new synthesizer architectures.Essential characteristics of a delay-locked loop (DLL), such as its first-order loop stability, relatively wide loop bandwidth, and low jitter accumulation, make DLL-based architectures attractive candidates for fast switching and low phase noise frequency synthesis applications. However, as an edge-combiner (EC) is required to produce different frequencies than that of the reference clock, any misalignment in equallyspaced DLL output edges will generate an erroneous periodicity, resulting in reference sideband spurs at the output spectrum of the frequency synthesizer.This thesis investigates the opportunities and challenges of employing DLL-based architectures to synthesize carrier frequencies for wireless applications, specifically UWB communication. The dissertation has contributed to two aspects of the topic; mathematical modeling and analysis, as well as circuit design and implementation.A comprehensive behavioral model of the harmonic spur levels in edge-combining DLL-based frequency synthesizers is developed which includes the effects of the stagedelay mismatch, the static phase error of the locked-loop, and the duty cycle distortion iv of the reference clock. Utilizing Fourier series representation of the DLL output phases, an analytical expression for synthesizer's spur levels is derived. Applying Taylor series approximations and moment methods to the analytical formula, closed-form expressions are obtained for the probability density function and mean value of the harmonic spur magnitudes. Finally, a Monte Carlo-free spur-aware design flow is introduced which significantly accelerates the iterative design procedure of the synthesizer. Accuracy and robustness of the prediction method against wide-range values of the non-idealities are investigated and verified through Monte Carlo simulations of the synthesizer's behavioral and transistor-level model in a 65-nm CMOS process.Three DLL-based architectures are developed and designed. In the first architecture, fast hopping frequency synthesis is achieve...

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Section: Direct Digital Synthesismentioning

confidence: 99%

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Ojani¹

2015

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“…Recently, integrated ultra-wideband (UWB) RF circuits have received considerable attention [24][25][26][27][28][29]. According to the Federal Communications Commission, the unlicensed frequency spectrum allocated for UWB systems is 3.1-10.6 GHz.…”

Section: Design Examplementioning

confidence: 99%

Analysis and design of common‐gate low‐noise amplifier for wideband applications

Kaukovuori¹,

Kaltiokallio²,

Ryynänen³

2008

Circuit Theory & Apps

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SUMMARYThe design of a common-gate (CG) LNA for the wideband applications is discussed in this paper. The effect of the different components in matching network is analyzed in detail. The design of a wideband input matching and output signal current for the input stage is presented. In addition, the effect of the matching network on the linearity and noise of a CG stage is studied. A design example is given to demonstrate the effectiveness of the presented theory.

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“…And the bandwidth of the each band is 528 MHz. The transceiver architecture was proposed as low-IF architecture or zero-IF architecture [1,2,3,4]. The center frequency of the 14-bands is from 3432 MHz to 10296 MHz, and the bandwidth of the band center frequency is 6864 MHz.…”

Section: Introductionmentioning

confidence: 99%

“…In paper [1], the frequency synthesizer adopts one VCO, four single-sideband (SSB) mixers, five frequency dividers, and two mux. In paper [2], the frequency synthesizer adopts two VCOs and four SSB mixers and two mux. In the paper [3], the frequency synthesizer adopts one VCO, five SSB mixers, five frequency dividers, and three mux.…”

Section: Introductionmentioning

confidence: 99%

Dual-band voltage controlled oscillator with optimized Gm

Huang

Chen

Hung

2015

IEICE Electron. Express

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A differential VCO with differential push-push frequency doubler for dual-band application is proposed. The dual-band VCO (DB-VCO) adopts the tunable −Gm to optimize the wide tuning start-up condition. The proposed DB-VCO was implemented in 180-nm CMOS process. The DB-VCO provides a fundamental center frequency at 4.476 GHz and a double frequency at 8.985 GHz. A tuning range of fundamental frequency is 1.125 GHz (3.928 GHz-5.053 GHz), and a tuning range of the double frequency is 2.257 GHz (7.856 GHz-10.113 GHz) with maximum control voltage of 1.0 V can be achieved. The phase noise is −96.0 dBc/Hz at 1 MHz offset from center of the DB-VCO fundamental frequency. And the phase noise is −86.4 dBc/Hz at 1 MHz offset from center of the DB-VCO double frequency. The power dissipation of the DB-VCO core is 6.6 mW through 1.0 V supply voltage. The active area is 0.09 mm 2 .

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A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

Cited by 64 publications

References 9 publications

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Analysis and Design of DLL-Based Frequency Synthesizers for Ultra-Wideband Communication

Analysis and design of common‐gate low‐noise amplifier for wideband applications

Dual-band voltage controlled oscillator with optimized Gm

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