Analysis and design of common‐gate low‐noise amplifier for wideband applications

A modified common source-common gate (CS-CG) low-noise transconductance amplifier (LNTA) with an improved noise figure (NF), operational bandwidth, and power consumption are analyzed in this paper. The common source (CS) stage of the modified LNTA is utilized for noise cancellation and transconductance enhancement of the common gate (CG) transistor. Using these, NF, bandwidth, and power consumption are improved without using extra active elements. Noise analyses show the modified CS-CG LNTA has lower NF than conventional CS-CG LNTA. The linearity of the modified CS-CG LNTA is calculated by Taylor series expression. Besides, a design procedure is proposed based on the obtained equations for linearity and NF. Finally, an ultra-wideband (UWB) surface acoustic wave (SAW-less) direct-conversion receiver is designed in 65 nm complementary metal-oxide-semiconductor (CMOS) technology. NF and third-order intercept point (IIP3) of the designed receiver are simulated as 5 dB and −2 dBm, respectively. The receiver consumes 18.4 mA from a 1.8 V supply voltage. KEYWORDS low noise amplifier (LNA), low-noise transconductance amplifier (LNTA), noise canceling LNTA, RF integrated circuits (RFIC), SAW-less receiver, ultra-wideband receiver 654

“…By calculating D 1 − D 3 , we can calculate the other variables such as A 1 − A 3 and B 1 − B 3 . Using this, we can obtain the Taylor coefficients of the differential output as 7,8…”

Section: Equation B14mentioning

confidence: 99%

A UWB receiver with modified CS‐CG LNTA: Noise and nonlinearity analysis

Javadi

Naimi

Andargoli

2019

“…CG LNAs 18–20 exhibit wide input impedance matching due to their topological nature. However, because of the matching condition that forces the g m of the main transistor to be 20 mS ( R in = 1/ g m ), NF does not yield better than (1 + γ/α) 21 . In order to increase the efficiency of the CG structure, some techniques are applied; for instance, Kim et al 18 reported a CG LNA with dual negative feedback.…”

Section: Introductionmentioning

confidence: 99%

“…However, because of the matching condition that forces the g m of the main transistor to be 20 mS (R in = 1/g m ), NF does not yield better than (1 + γ/α). 21 In order to increase the efficiency of the CG structure, some techniques are applied; for instance, Kim et al 18 reported a CG LNA with dual negative feedback. Due to off-chip components and high power consumption, however, their dual negative feedback scheme is not effective for low-power and wideband applications.…”

Section: Introductionmentioning

confidence: 99%

A low‐power wideband LNA exploiting current‐reuse and noise cancelation techniques

Khanehbeygi

Jafarnejad

Koozehkanani

et al. 2022

This paper presents an inductorless low-power wideband Low Noise Amplifier (LNA) in TSMC 0.18 μm CMOS technology. The proposed LNA is based on the Common-Gate (CG) topology, which consists of three consecutive stages: CG, Common-Source (CS), and Collector stage. The CG and CS configurations are responsible for providing the wideband input impedance matching and the majority of the gain, respectively. The overall performance of the LNA has been improved by applying noise cancelation, capacitive-peaking, and current reuse techniques. Unlike the conventional structure, the CG and CS sections' noise is canceled by utilizing a novel noise-canceling mechanism, simultaneously. Furthermore, with the capacitive-peaking technique, the voltage gain drop across hi gher frequencies is prevented, and thus, the bandwidth of the structure is improved. The trade-off between power consumption and input impedance has been dramatically resolved by employing the current reuse technique in the CG stage. Post-layout simulation results of the presented noise-canceling LNA demonstrate a Noise Figure (NF) of 2.19-2.58 dB and a maximum voltage gain of 19.84 dB with a À3 dB bandwidth of 0.2-2.85GHz. The simulated input/output matching (i.e., S11/S22) is better than À14.73/À19.43 dB in the entire bandwidth. Additionally, Input Third Intercept Point (IIP3) of À4.56 dBm is achieved. The results are gained by consuming only 2.87 mW under a supply voltage of 1.2 V and occupying a 0.0429 mm 2 of die area.

“…In order to improve the linearity, several techniques such as the differential multiple gated transistor linearization method , the feed‐forward distortion cancellation technique and the derivative superposition (DS) technique have been proposed . And in , the effect of the matching network on the linearity is analyzed. The DS technique, also known as multiple gated transistors, is a nonlinearity compensation method of transconductance.…”

Section: Introductionmentioning

confidence: 99%

A duplex current‐reused CMOS LNA with complementary derivative superposition technique

Dai

Zheng

et al. 2016

SUMMARYA duplex current-reused complementary metal-oxide-semiconductor low-noise amplifier (LNA) is proposed for 2.5-GHz application. The duplex current-reused topology with equivalent three common-source gain stages cascaded is utilized to fulfil the low-power consumption and high gain simultaneously. The complementary derivative superposition linearization technique with bulk-bias control is employed to improve the linearity performance with large-signal swing and to extend the auxiliary transistors bias-control range. The proposed LNA is fabricated in a 0.18-um 1P5M complementary metal-oxide-semiconductor process and consumes a 3.13-mA quiescent current from a 1.5 V voltage supply. The measurement results show that the proposed LNA achieves power gain of 28.1 dB, noise figure of 1.64 dB, input P1dB and IIP3 of À19.6 dBm and 3.2 dBm, respectively, while the input and output return loss is 19.2 dB and 18.4 dB.