A WideRange DelayLocked Loop with a Fixed Latency of One Clock Cycle

Abstract

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1 ( max ) to 1 (3 min ), where min and max are the minimum and maximum delay of a delay cell, respectively, and is the number of delay cells used in the delay line. Fabricated in a 0.35-m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 m 515 m and consumes a maximum power of 132 mW at 130 MHz.