A wideband CMOS LNA-mixer for cognitive radio receiver

Vitee, Nandini; Ramiah, Harikrishnan; Chong, Wee Khang

doi:10.1109/apccas.2014.7032791

Cited by 6 publications

(5 citation statements)

References 13 publications

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“…The gain equations are derived as a function of the equivalent RF voltage (V rf ) sensed at the source node of the input current sensing transistors. The analysis follows the methodology reported in [11,16,25]. The RF signal voltage (V rf ) with amplitude (A rf ) and frequency (ω rf ) in radians can be expressed as The IF signal in (4) can be simplified as where G O is the gain factor, and ω if is the frequency of the IF signal in radians and is expressed as…”

Section: Mixermentioning

confidence: 99%

“…To achieve the linearity requirements of the LR-WPAN direct-conversion systems using CS input stages, the firstorder transconductance ( g 1 m ) must be increased, or the thirdorder transconductance ( g 3 m ) must be reduced or nullified. Some of the common-source based RF down-converters are reported in [11][12][13][14][15][16][17]. In [11], 3.1-10.6 GHz RFDC is reported with 22.5 dB gain and − 11 dBm IIP3.…”

Section: Introductionmentioning

confidence: 99%

“…Some of the common-source based RF down-converters are reported in [11][12][13][14][15][16][17]. In [11], 3.1-10.6 GHz RFDC is reported with 22.5 dB gain and − 11 dBm IIP3. In [12], slightly lesser gain but improved linearity performance is reported with a power consumption of 24.5 mW.…”

Section: Introductionmentioning

confidence: 99%

“…In [19], linearity is compromised to yield a high gain of 38.4 dB and a noise figure of 16.7 dB. The high conversion gains reported in [11,13,15,19] will prove fruitful for reducing the overall noise figure of the wireless system and also helps to reduce the number of gain stages required in the receiver chain. High IIP3 provides a higher dynamic range for distortionless operation of the wireless system.…”

Section: Introductionmentioning

confidence: 99%

“…High IIP3 provides a higher dynamic range for distortionless operation of the wireless system. The trade-off sacrifices at least one of the performance parameters to gain the other in [11][12][13][14][15][16][17][18][19] while consuming large die area. However, modern deep sub-micron silicon process further complicates the gain and linearity trade-off in RF circuits.…”

Section: Introductionmentioning

confidence: 99%

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A 3-stage RF down-converter network for portable, wearable 5G applications

Gladson

Bhaskar

2019

SN Appl. Sci.

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The emerging 5G internet-of-things applications in home automation, smart wearables, healthcare monitoring, automotive sensors require low-cost, area efficient, high-performance and low power radio frequency blocks for effective short-range communication. This growing market demand is addressed in this paper by proposing a fully CMOS RF down-converter (RFDC) network for 5G applications. This work aims to achieve high linearity, low noise figure and high gain simultaneously by optimally splitting the performance between the three stages of the RFDC. The proposed downconversion system is designed in UMC 180 nm CMOS process technology and the post-layout simulations on layout extracted parameters with Cadence SpectreRF shows an IIP3 of − 3.43 dBm, an IIP2 of 78.13 dBm, double-sideband noise figure of 12.76 dB, a conversion gain of 23.69 dB, the spurious-free dynamic range of 71.7 dB, and the phase noise of − 91.39 dBc/Hz at an offset of 5 MHz. The proposed frequency translation circuit occupies a core area of only 0.0043 mm 2 and consumes a low power of 12.6 mW from a 1.8 V supply.

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Section: Mixermentioning

confidence: 99%